A Unified Transformer Architecture for Low-Latency and Scalable Wireless Signal Processing (2508.17960v1)

Abstract: We propose a unified Transformer-based architecture for wireless signal processing tasks, offering a low-latency, task-adaptive alternative to conventional receiver pipelines. Unlike traditional modular designs, our model integrates channel estimation, interpolation, and demapping into a single, compact attention-driven architecture designed for real-time deployment. The model's structure allows dynamic adaptation to diverse output formats by simply modifying the final projection layer, enabling consistent reuse across receiver subsystems. Experimental results demonstrate strong generalization to varying user counts, modulation schemes, and pilot configurations, while satisfying latency constraints imposed by practical systems. The architecture is evaluated across three core use cases: (1) an End-to-End Receiver, which replaces the entire baseband processing pipeline from pilot symbols to bit-level decisions; (2) Channel Frequency Interpolation, implemented and tested within a 3GPP-compliant OAI+Aerial system; and (3) Channel Estimation, where the model infers full-band channel responses from sparse pilot observations. In all cases, our approach outperforms classical baselines in terms of accuracy, robustness, and computational efficiency. This work presents a deployable, data-driven alternative to hand-engineered PHY-layer blocks, and lays the foundation for intelligent, software-defined signal processing in next-generation wireless communication systems.