A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals (2501.15275v1)

Abstract: As the conventional scaling of logic devices comes to an end, functional wafer backside and 3D transistor stacking are consensus for next-generation logic technology, offering considerable design space extension for powers, signals or even devices on the wafer backside. The Flip FET (FFET), a novel transistor architecture combining 3D transistor stacking and fully functional wafer backside, was recently proposed. With symmetric dual-sided standard cell design, the FFET can deliver around 12.5% cell area scaling and faster but more energy-efficient libraries beyond other stacked transistor technologies such as CFET. Besides, thanks to the novel cell design with dual-sided pins, the FFET supports dual-sided signal routing, delivering better routability and larger backside design space. In this work, we demonstrated a comprehensive FFET evaluation framework considering physical implementation and block-level power-performance-area (PPA) assessment for the first time, in which key functions are dual-sided routing and dual-sided RC extraction. A 32-bit RISC-V core was used for the evaluation here. Compared to the CFET with single-sided signals, the FFET with single-sided signals achieved 23.3% post-P&R core area reduction, 25.0% higher frequency and 11.9% lower power at the same utilization, and 16.0 % higher frequency at the same core area. Meanwhile, the FFET supports dual-sided signals, which can further benefit more from flexible allocation of cell input pins on both sides. By optimizing the input pin density and BEOL routing layer number on each side, 10.6% frequency gain was realized without power degradation compared to the one with single-sided signal routing. Moreover, the routability and power efficiency of FFET barely degrades even with the routing layer number reduced from 12 to 5 on each side, validating the great space for cost-friendly design enabled by FFET.

• The paper evaluates the Flip FET (FFET) architecture's physical implementation and block-level PPA performance, demonstrating significant advantages over CFET enabled by novel dual-sided signal routing.
• Utilizing a RISC-V core on a virtual 5nm node, FFET showed a 23.3% core area reduction, 25% frequency gain, and 11.9% power reduction compared to CFET.
• FFET's symmetric dual-sided cell design and routing facilitate dense configurations and enhanced performance, positioning it as a promising candidate for future logic scaling and high-performance computing.

Physical Implementation and Block-Level PPA Evaluation of Flip FET with Dual-Sided Signals

The paper in question explores the evaluation of a novel transistor architecture, the Flip FET (FFET), contrasting its performance with established technologies such as the Complementary FET (CFET). The authors offer an in-depth analysis focusing on both physical implementation and block-level power-performance-area (PPA) characteristics through dual-sided signal routing and dual-sided RC extraction. The authors have utilized a 32-bit RISC-V core for empirical validation, demonstrating the potential advantages the FFET architecture possesses over current transistor stacking methodologies.

Key Contributions

The FFET, characterized by its symmetric dual-sided standard cell design, is created with considerations for dual-sided signal routing. It allows for a dense cell configuration, achieving approximately 12.5% cell area scaling when compared to existing transistor technologies. Furthermore, within the paper, the FFET demonstrated a 23.3% core area reduction, a 25% improvement in frequency, and an 11.9% reduction in power consumption compared to CFET at equivalent utilization and conditions.

The architecture involves a unique symmetric cell design achieved by employing intra-cell signals and power rails on both sides, allowing backend-of-line (BEOL) routing layers without bridging cells. Key innovations include the Power Tap Cells, optimized power planning schemes, and dual-sided RC net extraction methodologies.

Analytical Framework

The research outlines a comprehensive FFET evaluation framework, notably involving:

• Dual-Sided Signal Routing: This concept fundamentally allows logic gates to output pins on both frontside and backside signal tracks, facilitating convenient routing options for circuits without bridging cells.
• Power Planning and Power Tap Cells: SPDN integrated with FFET is managed via Power Tap Cells that connect frontside and backside power distributions effectively, maintaining power integrity across the structure.
• Evaluation of Input Pin Density and BEOL Routing Layers: By optimally distributing input pin density and finely adjusting routing layers, FFET achieves an additional 10.6% frequency gain, enhancing performance without added power consumption.

Experimental Results and Discussion

Utilizing a virtual 5 nm node process design kit (PDK), the FFET's library was characterized to enable direct performance comparisons. The findings show that FFET cells outperform 4T CFET cells regarding timing attributes and power efficiency, thanks in large part to reduced parasitic effects and the advantage in intra-cell structure.

To ensure robust data driven evaluation, the design strategy was employed to explore the viable design space of FFETs differing DM characteristics, offered significant PPA improvements. Given varying backend-of-line (BEOL) routing layers, input pin configurations, and adjustment of frontend and backend routing capabilities, the research illuminated novel paths for cost-effective and high-performance computing enhancements.

Implications and Future Directions

Detailed analysis of dual-sided signal routing demarcates the FFET as a promising candidate for future semiconductor advancements given its potential to sustain logic scaling. By offering additional design flexibility, higher resource efficiency, and lower power demands, the FFET could significantly impact high-performance computing domains.

While the paper is empirical and theoretical frameworks are well-anchored on present technology trends, future work could examine extensions to even lower nm node processes and broader functional simulation models. Verification through fabrication and real-world testing would further confirm FFET's proposed efficiencies and route its application in advanced processor designs, validating its place in the continuation and expansion of Moore's Law.

In summary, this paper systematically outlines the beneficial properties of FFET architecture in the context of semiconductor technology scaling, presenting a robust case for its performance advantages over CFET in both cell and block-level assessments. The dual-sided routing innovation, coupled with optimizations in power distribution and cell design presents a progressive route for future electronic design automation (EDA) enhancements.