Hardware-efficient quantum error correction via concatenated bosonic qubits (2409.13025v2)

Abstract: In order to solve problems of practical importance, quantum computers will likely need to incorporate quantum error correction, where a logical qubit is redundantly encoded in many noisy physical qubits. The large physical-qubit overhead typically associated with error correction motivates the search for more hardware-efficient approaches. Here, using a microfabricated superconducting quantum circuit, we realize a logical qubit memory formed from the concatenation of encoded bosonic cat qubits with an outer repetition code of distance $d=5$. The bosonic cat qubits are passively protected against bit flips using a stabilizing circuit. Cat-qubit phase-flip errors are corrected by the repetition code which uses ancilla transmons for syndrome measurement. We realize a noise-biased CX gate which ensures bit-flip error suppression is maintained during error correction. We study the performance and scaling of the logical qubit memory, finding that the phase-flip correcting repetition code operates below threshold, with logical phase-flip error decreasing with code distance from $d=3$ to $d=5$. Concurrently, the logical bit-flip error is suppressed with increasing cat-qubit mean photon number. The minimum measured logical error per cycle is on average $1.75(2)\%$ for the distance-3 code sections, and $1.65(3)\%$ for the longer distance-5 code, demonstrating the effectiveness of bit-flip error suppression throughout the error correction cycle. These results, where the intrinsic error suppression of the bosonic encodings allows us to use a hardware-efficient outer error correcting code, indicate that concatenated bosonic codes are a compelling paradigm for reaching fault-tolerant quantum computation.

• The paper demonstrates that concatenated bosonic cat qubits, with inherent noise bias, significantly reduce hardware overhead in quantum error correction.
• It employs a repetition code (distance-5) and a noise-biased CX gate to effectively suppress phase-flip errors while naturally reducing bit-flip errors.
• Empirical results show a marked decrease in logical phase-flip error rates, paving the way for scalable, fault-tolerant quantum computation.

Overview of "Hardware-efficient quantum error correction using concatenated bosonic qubits"

The paper "Hardware-efficient quantum error correction using concatenated bosonic qubits" presents a significant advancement in the domain of quantum error correction (QEC) for quantum computing. The authors focus on optimizing the hardware requirements necessary for implementing QEC through concatenated bosonic qubits, using a novel approach involving bosonic cat qubits in conjunction with a repetition code. This methodology is executed within a superconducting quantum circuit framework. The primary goal is to alleviate the substantial overhead traditionally associated with QEC implementations in superconducting systems.

Key Developments and Findings

1. Bosonic Cat Qubits and Error Protection: The researchers leverage bosonic cat qubits, which naturally exhibit noise bias favoring bit-flip suppression. This is accomplished by storing quantum information across several cat qubits, i.e., states characterized by low bit-flip error rates but susceptible to phase-flip errors. The bosonic basis allows cat qubits to harness the vast Hilbert space of a quantum harmonic oscillator, thereby reducing hardware demands.
2. Use of Repetition Code: Complementing the intrinsic noise bias of bosonic cat qubits, the paper employs a repetition code to correct phase-flip errors. Specifically, they implement a replication code of distance 5, empirically demonstrating that while phase errors are error-corrected, bit-flip errors remain naturally suppressed due to the encoding through bosonic cat codes.
3. CX Gate and Noise Bias: The paper highlights the development and application of a noise-biased CX (controlled-X) gate, which is essential for maintaining noise bias during syndrome measurements. The gate utilizes an ancilla encoded in the transmon's energy levels, with effective $\chi$-matching to mitigate deleterious ancilla decay events that could propagate errors.
4. Logical Qubit Memory: The experimentation suggests that concatenated bosonic codes contribute to fault-tolerant quantum computation by providing a hardware-efficient pathway to logical qubit memory. The implemented system showcases bit-flip and phase-flip properties optimized by error-correction mechanisms, resulting in an effective cyclic logical error rate.
5. Minimum Logical Error Rates: Empirical results communicated in the paper indicate that the logical phase-flip probability per cycle saw a marked decrease as the repetition code was scaled from distance-3 to distance-5. Concurrently, the bit-flip error was shown to decrease with increasing mean photon numbers of the bosonic cat qubits.

Implications and Future Directions

The findings signify a leap toward more scalable quantum error correction techniques by reducing the substantial resource overhead previously requisite in practical applications. This work presents a valuable intermediary step preceding full-fledged quantum fault tolerance and error normalization required for scalable quantum computations.

Implications for Quantum Computing:

• The results endorse bosonic encodings as robust solutions for error suppression in noisy quantum hardware.
• The hardware efficiency yields a crucial advantage in practical quantum computing implementations, supporting applications in quantum chemistry, cryptography, and complex material simulations.

Future Research:

• Expanding upon this experiment's results could involve scaling the concatenated bosonic architecture further, potentially integrating enhanced surface codes tailored for noise-biased systems.
• Continued efforts toward engineering genuinely bias-preserving gates should be entertained, as these might significantly augment the efficacy and threshold capabilities of QEC circuits.
• The paper opens avenues for refining the interactions between hardware components, primarily focusing on minimizing cross-talk and parasitic effects that could compromise measurement fidelity.

Conclusion

By bridging the gap between theory and application, this work showcases that complex error correction can be embedded in efficient hardware, pointing toward practical fault-tolerant quantum computing strategies. The pursuit of bias-preserving quantum gates, combined with bosonic error-correction codes, marks a promising direction in minimizing error rates while maximizing scalable quantum processor capacities.