Logical multi-qubit entanglement with dual-rail superconducting qubits
(2504.12099v1)
Published 16 Apr 2025 in quant-ph
Abstract: Recent advances in quantum error correction (QEC) across hardware platforms have demonstrated operation near and beyond the fault-tolerance threshold, yet achieving exponential suppression of logical errors through code scaling remains a critical challenge. Erasure qubits, which enable hardware-level detection of dominant error types, offer a promising path toward resource-efficient QEC by exploiting error bias. Single erasure qubits with dual-rail encoding in superconducting cavities and transmons have demonstrated high coherence and low single-qubit gate errors with mid-circuit erasure detection, but the generation of multi-qubit entanglement--a fundamental requirement for quantum computation and error correction--has remained an outstanding milestone. Here, we demonstrate a superconducting processor integrating four dual-rail erasure qubits that achieves the logical multi-qubit entanglement with error-biased protection. Each dual-rail qubit, encoded in pairs of tunable transmons, preserves millisecond-scale coherence times and single-qubit gate errors at the level of $10{-5}$. By engineering tunable couplings between logical qubits, we generate high-fidelity entangled states resilient to physical qubit noise, including logical Bell states (98.8% fidelity) and a three-logical-qubit Greenberger-Horne-Zeilinger (GHZ) state (93.5% fidelity). A universal gate set is realized through a calibrated logical controlled-NOT (CNOT) gate with 96.2% process fidelity, enabled by coupler-activated $XX$ interactions in the protected logical subspace. This work advances dual-rail architectures beyond single-qubit demonstrations, providing a blueprint for concatenated quantum error correction with erasure qubits.
Summary
The paper demonstrates high-fidelity logical multi-qubit entanglement using dual-rail superconducting qubits integrated into a specialized processor.
Single logical qubit operations achieved a logical T1 of 0.98 ms and gate errors of 10
The paper demonstrates high-fidelity logical multi-qubit entanglement using dual-rail superconducting qubits integrated into a specialized processor.
Achieving logical Bell states with 98.8% fidelity and a three-qubit GHZ state with 93.5% fidelity marks a significant step towards practical fault-tolerant quantum computation.
Logical Multi-Qubit Entanglement with Dual-Rail Superconducting Qubits
The paper Logical multi-qubit entanglement with dual-rail superconducting qubits is a significant contribution to the domain of quantum computing, demonstrating advancements in quantum error correction (QEC) using dual-rail qubits in superconducting circuits. The authors present a superconducting quantum processor that integrates four dual-rail erasure qubits, facilitating high fidelity entangled states through tamed error-biased protection, marking a progression towards scalable error correction codes with practical quantum computational applications.
Processor Architecture and Dual-Rail Encoding
The experimental setup employs flip-chip integration of a qubit chip and a carrier chip to house four logical qubits. Each logical qubit is comprised of pairs of tunably coupled transmons, thus forming the dual-rail encoding. This dual-rail encoding leverages the hybridization of transmon pairs to establish logical states with prolonged coherence times and suppressed noise through passive dynamical decoupling. The encoded qubits allow T1 errors, which primarily manifest as decay into non-computational states, to be detected and corrected as erasures, thus enhancing the error threshold of QEC protocols.
Single-Qubit Operations and Erasure Detection
The research reports notable metrics in single-qubit operations within the logical subspace. A logical T1 of approximately 0.98 ms, alongside highly efficient single-qubit logical gate operations with gate errors measured at 10−5, underline the robustness achieved in the logical states. The utilization of an ancilla qubit for mid-circuit erasure checks further extends the operational integrity by effectively identifying and discarding erroneous computation paths.
Generation of Multi-Qubit Entanglement
The dual-rail processor conducts high-fidelity entangled state production using logical qubits, which is foundational for the execution of scalable quantum algorithms and effective QEC. The implementation of a logical CNOT gate, synthesized from logical iSWAP gates, permits the construction of universal gate sets necessary for such computations. The experimental observation of logical Bell states with 98.8% fidelity and the creation of a three-logical-qubit Greenberger-Horne-Zeilinger (GHZ) state with 93.5% fidelity highlights a crucial leap in logical entanglement capabilities.
Coherence and Error Management
Coherence preservation without active error correction, with logical Bell states sustaining fidelity above 70% beyond 100 μs, exemplifies the intrinsic error mitigation afforded by dual-rail architectures. Despite operating under the constraints of coherence-limited gate fidelity potentials above 99.9%, current practical realizations show room for optimization, particularly concerning coupler-induced decoherence mitigations during logical CNOT operations.
Future Implications and Developments
This work establishes a reliable framework for dual-rail architectures that indicate viable pathways for practical QEC implementations via concatenated code strategies. Moreover, the findings suggest potential enhancements in quantum network applications and precision quantum metrology by leveraging the dual-rail encoding for extended fidelity entangled state retention. Continued advancement may focus on refining coupling mechanisms and gate pulse sequences to further lift logical gate performance towards error correction thresholds, thus fortifying the scalability prospects of superconducting quantum processors.
In conclusion, the presented dual-rail system not only meets a critical benchmark in the quest for fault-tolerant quantum computation but sets the stage for the next phases of exploration in superconducting circuit platforms, enabling more intricate and resource-efficient quantum information processing protocols.