An RRAM-Based Implementation of a Template Matching Circuit for Low-Power Analogue Classification (2303.02651v3)

Abstract: Recent advances in machine learning and neuro-inspired systems enabled the increased interest in efficient pattern recognition at the edge. A wide variety of applications, such as near-sensor classification, require fast and low-power approaches for pattern matching through the use of associative memories and their more well-known implementation, Content Addressable Memories (CAMs). Towards addressing the need for low-power classification, this work showcases an RRAM-based analogue CAM (ACAM) intended for template matching applications, providing a low-power reconfigurable classification engine for the extreme edge. The circuit uses a low component count at 6T2R2M, comparable with the most compact existing cells of this type. In this work, we demonstrate a hardware prototype, built with commercial off-the-shelf (COTS) components for the MOSFET-based circuits, that implements rows of 6T2R2M employing TiOx-based RRAM devices developed in-house, showcasing competitive matching window configurability and definition. Furthermore, through simulations, we validate the performance of the proposed circuit by using a commercially available 180nm technology and in-house RRAM data-driven model to assess the energy dissipation, exhibiting 60 pJ per classification event.