Tiramisu: A Polyhedral Compiler for Expressing Fast and Portable Code (1804.10694v5)

Abstract: This paper introduces Tiramisu, a polyhedral framework designed to generate high performance code for multiple platforms including multicores, GPUs, and distributed machines. Tiramisu introduces a scheduling language with novel extensions to explicitly manage the complexities that arise when targeting these systems. The framework is designed for the areas of image processing, stencils, linear algebra and deep learning. Tiramisu has two main features: it relies on a flexible representation based on the polyhedral model and it has a rich scheduling language allowing fine-grained control of optimizations. Tiramisu uses a four-level intermediate representation that allows full separation between the algorithms, loop transformations, data layouts, and communication. This separation simplifies targeting multiple hardware architectures with the same algorithm. We evaluate Tiramisu by writing a set of image processing, deep learning, and linear algebra benchmarks and compare them with state-of-the-art compilers and hand-tuned libraries. We show that Tiramisu matches or outperforms existing compilers and libraries on different hardware architectures, including multicore CPUs, GPUs, and distributed machines.

• The paper presents a novel four-level IR that separates algorithm specification from optimizations, enhancing portability across diverse hardware architectures.
• The paper introduces a rich scheduling language that enables explicit control over computations, data communication, and memory hierarchy mappings.
• The paper demonstrates up to a 2.3× speedup over Intel MKL in convolution and matrix multiplications, underscoring its high-performance design.

Critical Review of "Tiramisu: A Polyhedral Compiler for Expressing Fast and Portable Code"

The paper "Tiramisu: A Polyhedral Compiler for Expressing Fast and Portable Code" presents the design and implementation of Tiramisu, a polyhedral framework aimed at generating high-performance code across diverse platforms including multicores, GPUs, and distributed systems. This paper addresses several complex challenges inherent in modern computing architectures, such as efficient code generation and memory management across different hardware backends.

The authors introduce a novel scheduling language within Tiramisu, which enables explicit management of computations, providing fine-grained control over various optimizations. This helps in handling intricacies associated with targeting a wide range of systems. Tiramisu particularly focuses on domains like image processing, stencils, linear algebra, and deep learning, where data parallel algorithms are prevalent.

Key Features and Contributions

A significant contribution of this work is the adoption of a four-level Intermediate Representation (IR) that separates algorithm specification from optimizations and data-layout transformations. This separation mitigates the complexity traditionally associated with the polyhedral model, facilitating easier targeting of multiple hardware architectures. Such a distinction allows Tiramisu to manage computational orders and data flows without the need to rearrange memory-based dependencies until the final stages of compilation, enhancing portability and flexibility.

Another highlighted feature is the rich scheduling language of Tiramisu, which introduces unique commands for controlling data communication, synchronization, and memory hierarchy mappings. These commands provide users with a potent toolbox to explore and exploit the capabilities of high-performance architectures effectively.

Methodological Approach

The paper methodically outlines the transition from high-level algorithmic descriptions to optimized code generation through transformations across its IR layers. The scheduling commands allow users to dictate loop transformations, map computations across hardware hierarchies, and manage data layout — all systematically handled within the IR. Tiramisu also supports non-affine accesses and cyclic data flows, showcasing the robustness of its dependence analysis.

Comparative Evaluation

The authors evaluate Tiramisu against state-of-the-art frameworks and libraries, such as Halide, Intel's Math Kernel Library (MKL), and distributed Halide, among others. The results demonstrate that Tiramisu matches or surpasses the performance of existing solutions, including hand-optimized libraries like Intel MKL, underlining its efficacy. The paper provides strong numerical results, particularly with convolution operations and matrix multiplications, where Tiramisu shows up to a $2.3\times$ speedup over Intel MKL.

Implications and Future Directions

The implications of Tiramisu in the area of high-performance computing are profound. By simplifying the code generation process for complex architectures, Tiramisu enables researchers and developers to focus on algorithmic optimizations without getting bogged down by hardware-specific details.

Theoretically, Tiramisu lays groundwork driving further development and exploration of polyhedral models in compiler design. Practically, as computing systems become increasingly heterogeneous, the ability of Tiramisu to portably and efficiently target diverse architectures holds significant promise.

In future advancements, expanding the domains targeted by Tiramisu beyond dense array operations to sparse computations and irregular data structures could be beneficial. Furthermore, incorporating adaptive tuning mechanisms based on runtime performance can potentially enhance its optimization decisions dynamically.

Conclusion

The introduction of Tiramisu offers a compelling testament to the ongoing need for adaptable, portable, and high-performance compiler frameworks. The paper portrays not only the effectiveness of a polyhedral approach but also emphasizes the importance of layered abstractions in dealing with the growing complexity of computational hardware. As such, Tiramisu serves as a crucial step towards realizing efficient and scalable high-performance systems in diverse computing environments.