All-in-Memory Stochastic Computing using ReRAM (2504.08340v1)

Abstract: As the demand for efficient, low-power computing in embedded and edge devices grows, traditional computing methods are becoming less effective for handling complex tasks. Stochastic computing (SC) offers a promising alternative by approximating complex arithmetic operations, such as addition and multiplication, using simple bitwise operations, like majority or AND, on random bit-streams. While SC operations are inherently fault-tolerant, their accuracy largely depends on the length and quality of the stochastic bit-streams (SBS). These bit-streams are typically generated by CMOS-based stochastic bit-stream generators that consume over 80% of the SC system's power and area. Current SC solutions focus on optimizing the logic gates but often neglect the high cost of moving the bit-streams between memory and processor. This work leverages the physics of emerging ReRAM devices to implement the entire SC flow in place: (1) generating low-cost true random numbers and SBSs, (2) conducting SC operations, and (3) converting SBSs back to binary. Considering the low reliability of ReRAM cells, we demonstrate how SC's robustness to errors copes with ReRAM's variability. Our evaluation shows significant improvements in throughput (1.39x, 2.16x) and energy consumption (1.15x, 2.8x) over state-of-the-art (CMOS- and ReRAM-based) solutions, respectively, with an average image quality drop of 5% across multiple SBS lengths and image processing tasks.

All-in-Memory Stochastic Computing using ReRAM

In the article "All-in-Memory Stochastic Computing using ReRAM," the authors pursue the development of energy-efficient and high-throughput stochastic computing (SC) architectures by leveraging novel memory technologies such as resistive random-access memory (ReRAM). This paper addresses the necessity for enhanced computational models in the expanding context of embedded and edge applications, where traditional computing paradigms struggle to meet the demands of modern complexity due to constraints of power and area.

Background and Motivation

Traditional von Neumann computing architecture often fails under resource constraints posed by state-of-the-art embedded systems, which can involve intensive tasks like image processing and neural network computations. Stochastic computing presents an interesting opportunity in this area through its unique computation system that encodes information in random bit-streams, allowing complex operations to be performed with simple digital logic while maintaining inherent noise resilience. However, the external generation of these bit-streams predominantly through CMOS technology significantly constrains energy efficiency, accounting for up to 80% of total energy consumption in SC systems.

Methodology and Contributions

This paper extends conventional stochastic computing by proposing an all-in-memory SC solution that fully integrates the generation, manipulation, and conversion of stochastic bit-streams (SBSs) into a ReRAM-based compute-in-memory (CIM) architecture. Key contributions include:

1. Complete In-Memory SC Flow: The architecture integrates RNG generation, SC operations, and conversion back to binary all within the ReRAM framework. This eliminates unnecessary data movement between memory and processor, typical in conventional setups.
2. RNG-Decoupled SBS Generation: Introducing a method that decouples RNG generation from SBS generation enables the potential use of various RNG types, including true RNGs built on ReRAM's properties.
3. Novel Conversion Techniques: An in-memory conversion method capable of producing SBSs with specific probabilities from binary sequences and performing SC operations, leveraging the intrinsic variability and density of ReRAM devices.
4. Efficiency and Robustness: The proposed system exhibits throughput improvements of 1.39x and energy reductions of up to 2.8x over existing technologies while maintaining a fault-tolerant design that reduces the need for extensive error correction and protection systems within ReRAM memories.

Results and Implications

The empirical results presented suggest significant enhancements in both processing throughput and energy efficiency across evaluation benchmarks. Practical applications, such as image processing tasks, illustrate the efficacy of the proposed methods. The proposed architecture enhances the fault tolerance of SC operations, with an average quality drop of only 5% in presence of faults compared to traditional methods that experience nearly 47% degradation.

Future Directions

This exploration of in-memory computing using emerging memory technologies opens up pathways for further research into optimizing ReRAM variability and exploring other nonvolatile memories for SC systems. As these architectures mature, their intersection with edge computing and AI applications could provide critical advancements in making state-of-the-art computing more accessible and sustainable. Future work may also further address scaling challenges and explore trade-offs in SBS generation and conversion within different application domains.

In conclusion, the paper presents a thorough examination and novel contributions to stochastic computing frameworks using resistive memory technologies, displaying notable advancements in throughput and energy efficiency, and strengthens the foundation for practical and robust implementations in the field of edge and embedded computing.