GraphR: Accelerating Graph Processing Using ReRAM (1708.06248v4)

Abstract: This paper presents GRAPHR, the first ReRAM-based graph processing accelerator. GRAPHR follows the principle of near-data processing and explores the opportunity of performing massive parallel analog operations with low hardware and energy cost. The analog computation is suit- able for graph processing because: 1) The algorithms are iterative and could inherently tolerate the imprecision; 2) Both probability calculation (e.g., PageRank and Collaborative Filtering) and typical graph algorithms involving integers (e.g., BFS/SSSP) are resilient to errors. The key insight of GRAPHR is that if a vertex program of a graph algorithm can be expressed in sparse matrix vector multiplication (SpMV), it can be efficiently performed by ReRAM crossbar. We show that this assumption is generally true for a large set of graph algorithms. GRAPHR is a novel accelerator architecture consisting of two components: memory ReRAM and graph engine (GE). The core graph computations are performed in sparse matrix format in GEs (ReRAM crossbars). The vector/matrix-based graph computation is not new, but ReRAM offers the unique opportunity to realize the massive parallelism with unprecedented energy efficiency and low hardware cost. With small subgraphs processed by GEs, the gain of performing parallel operations overshadows the wastes due to sparsity. The experiment results show that GRAPHR achieves a 16.01x (up to 132.67x) speedup and a 33.82x energy saving on geometric mean compared to a CPU baseline system. Com- pared to GPU, GRAPHR achieves 1.69x to 2.19x speedup and consumes 4.77x to 8.91x less energy. GRAPHR gains a speedup of 1.16x to 4.12x, and is 3.67x to 10.96x more energy efficiency compared to PIM-based architecture.

• The paper introduces GraphR, a novel architecture that accelerates graph processing by leveraging Resistive RAM (ReRAM) for near-data analog computation.
• GraphR exploits ReRAM crossbars to efficiently perform sparse matrix-vector multiplications, a key operation in many graph algorithms, through in-situ analog computation.
• Evaluation shows GraphR achieves significant speedups (16.01 ataset geometric average) and energy savings (around 33.82 ataset) compared to CPU baselines by reducing data movement.

Overview of "GraphR: Accelerating Graph Processing Using ReRAM"

The paper "GraphR: Accelerating Graph Processing Using ReRAM," explores leveraging Resistive RAM (ReRAM) technology to address the inefficiencies in conventional graph processing architectures. Graph processing often suffers from high memory bandwidth requirements and poor locality, which are exacerbated by significant data movements and energy consumption. Graph processing accelerators typically focus on memory access optimizations or incorporate computational logic close to memory. In contrast, GraphR adopts a fundamentally different approach by exploiting ReRAM for near-data processing through analog computation, which is particularly well-suited for the iterative nature and error resilience characteristic of many graph algorithms.

Core Contributions

1. ReRAM-based Architecture: GraphR introduces a novel accelerator architecture composed of memory ReRAM for data storage and Graph Engines (GE) for computation. A core insight is that a broad class of graph algorithms can be expressed as sparse matrix vector multiplications (SpMV), which ReRAM crossbars can perform efficiently. This realization enables substantial energy efficiency and performance improvement due to ReRAM's in-situ computing capabilities.
2. Analog Computation with ReRAM: GraphR capitalizes on the analog nature of ReRAMs, where computations are performed in the memory itself, thus reducing data movement—a primary source of inefficiency in graph processing tasks. ReRAM's suitability for graph processing arises from two key algorithmic attributes: tolerance to numerical imprecision and resilience in integer-based operations, such as those found in algorithms like BFS and SSSP.
3. Design and Implementation: The architecture integrates ReRAM crossbars with a streaming-apply execution model, which processes graph data in subgraphs. Data is converted from a compressed sparse format for storage to a sparse matrix format for processing, increasing computation to data movement ratio. The design includes a hardware framework for ReRAM crossbars connected through components like Drivers, ADCs, and lightweight ALUs for necessary operations and optimizations.
4. Performance Evaluation: Experimental results are notable, showing GraphR achieves significant speedups, with a geometric average of 16.01× (up to 132.67×) over a conventional CPU baseline. Energy savings are also impressive, typically about 33.82× over the CPU baseline configuration. When compared to GPU and PIM-based architectures, GraphR retains a competitive edge in energy consumption and computational throughput.

Implications and Future Directions

GraphR significantly pushes the envelope on what is achievable through hardware acceleration for graph processing by leveraging emerging memory technologies. The shift to analog computation presents an innovative frontier for graph processing, offering a pathway to unlock higher efficiencies in both speed and energy use. The research also opens up several avenues for enhanced AI applications where graph data structures are prevalent, such as large-scale social networks, bioinformatics, and recommendation systems.

Looking towards future developments, explorations may focus on optimizing the ReRAM technology further for larger-scale deployments, integrating with distributed graph processing systems, and extending the model to additional graph algorithmic paradigms. As ReRAM and other non-volatile memory technologies mature, their application in diverse computational problems will likely expand, reflecting the growing convergence of memory and processor technologies.

Conclusion

The GraphR architecture stands as a testament to the innovative potential of near-data processing and the benefits of analog computation in graph processing. By effectively leveraging ReRAM, the paper contributes a compelling solution to a significant computational challenge, promising significant ramifications in efficiency-critical domains.