A photonic integrated processor for multiple parallel computational tasks (2501.18186v1)

Abstract: Optical networks with parallel processing capabilities are significant in advancing high-speed data computing and large-scale data processing by providing ultra-width computational bandwidth. In this paper, we present a photonic integrated processor that can be segmented into multiple functional blocks, to enable compact and reconfigurable matrix operations for multiple parallel computational tasks. Fabricated on a silicon-on-insulator (SOI) platform, the photonic integrated processor supports fully reconfigurable optical matrix operations. By segmenting the chip into multiple functional blocks, it enables optical matrix operations of various sizes, offering great flexibility and scalability for parallel computational tasks. Specifically, we utilize this processor to perform optical convolution operations with various kernel sizes, including reconfigurable three-channel 1x1 convolution kernels and 2x2 real-valued convolution kernels, implemented within distinct segmented blocks of the chip. The multichannel optical 1x1 convolution operation is experimentally validated by using the deep residual U-Net, demonstrating precise segmentation of pneumonia lesion region in lung CT images. In addition, the capability of the 2x2 optical convolution operation is also experimentally validated by constructing an optical convolution layer and integrating an electrical fully connected layer, achieving ten-class classification of handwritten digit images. The photonic integrated processor features high scalability and robust parallel computational capability, positioning it a promising candidate for applications in optical neural networks.