A 64-Channel Precision Time-to-Digital Converter with Average 4.77 ps RMS Implemented in a 28 nm FPGA (2412.18642v1)

Abstract: We have developed a Time-to-Digital Converter (TDC) application in a Xilinx Kintex-7 Field Programmable Gate Array (FPGA). This TDC, based on the Tapped-Delay Line (TDL) and Wave Union A (WU-A) techniques, achieves an independent time measurement on 32-channel rising edges and 32-channel falling edges. The average time resolution or the Least Significant Bit (LSB) of the 64 channels is measured to be 3 ps level, with an average root mean square (RMS) precision of 4.77 ps, and a maximum RMS below 8 ps. We also propose an online processing scheme that handles the bubble issues caused by clock region skew.