Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS (2406.15107v1)

Abstract: Open-source hardware (OSHW) is rapidly gaining traction in academia and industry. The availability of open RTL descriptions, EDA tools, and even PDKs enables a fully auditable supply chain for end-to-end (RTL to layout) open-source silicon, significantly strengthening security and transparency. Despite promising developments, existing OSHW efforts have so far fallen short of producing end-to-end open-source SoCs at the complexity and performance level needed to run a general-purpose OS. We present Basilisk, the first end-to-end open-source, Linux-capable RISC-V SoC taped out in IHP's open 130 nm technology. Basilisk features a 64-bit RISC-V core, a fully digital HyperRAM DRAM controller, and a rich set of IO peripherals including USB 1.1 and VGA. To tape out Basilisk, we create a reusable tool pipeline to convert its industry-grade SystemVerilog description to Verilog. We optimized logic synthesis in the open source Yosys synthesis tool, obtaining an increase in Basilisk's peak clock speed by 2.3x to 77 MHz and reducing its cell area by 1.6x to 1.1 MGE while also reducing synthesis runtime and RAM usage. We further optimized place and route in OpenROAD, enabling convergence to zero DRC violations while increasing core area utilization by 10% and reducing die area by 12%.

• The paper presents Basilisk, an open-source Linux-capable RISC-V SoC built around a 64-bit RV64GC CVA6 core with diverse digital peripherals.
• It details a novel synthesis pipeline using SVase and enhanced Yosys optimizations that boost clock speed from 33 MHz to 77 MHz while reducing cell area.
• The design achieves zero DRC violations and improved core utilization through refined power grid design and physical implementation during the place and route process.

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS

This paper introduces Basilisk, a significant milestone in the open-source hardware (OSHW) community, detailing the development and implementation of the first end-to-end open-source, Linux-capable RISC-V system-on-chip (SoC) utilizing IHP's 130nm CMOS technology. This essay discusses the critical architecture, toolchain optimizations, and the implications of such advancements within the field of OSHW.

Architectural Overview

Basilisk is built around the energy-efficient RV64GC CVA6 core, leveraging the open-source Cheshire SoC platform. Key components of the SoC include a 64-bit RISC-V core, a fully digital HyperRAM DRAM controller, and a broad array of input/output peripherals such as USB 1.1 and VGA. The SoC architecture is designed to maximize both performance and versatility, featuring a two-stage interconnect system that integrates an AXI4 crossbar and a Regbus demultiplexer to manage various data throughput requirements.

Notably, Basilisk incorporates a fully digital HyperRAM DRAM controller capable of handling two chips with transfer speeds up to 154 MB/s, coupled with an L1 instruction and data cache configuration. The inclusion of diverse peripherals—ranging from I2C and SPI to USB 1.1 OHCI and VGA controllers—ensures comprehensive Linux compatibility and practical usability in real-world systems. Additionally, the SoC is equipped with a JTAG test access point and a high-efficiency asynchronous DMA engine, enhancing its debugging and data transfer capabilities respectively.

Synthesis and Optimization

In developing Basilisk, the authors introduced a reusable tool pipeline to convert industry-grade SystemVerilog (SV) code into Verilog compatible with Yosys synthesis tools. SVase, a source-to-source parameter-resolving SV pre-elaborator leveraging the Slang library, plays a pivotal role in preprocessing the SV RTL description for synthesis. This pipeline ensures accurate parameter resolution and instance dependency removal, optimizing the SV code for subsequent processing.

Significant enhancements to Yosys' logic synthesis were made, including:

• Part-Select Synthesis Optimization: Transitioning indexed part-select operations to more efficient block-multiplexer trees.
• Lazy Man's Synthesis (LMS): Incorporating precomputed, optimized logic implementations from ABC into the synthesis process.
• Library of Arithmetic Units: Implementing optimized arithmetic unit libraries for more efficient MAC and FMA operations.

These optimizations collectively improved the peak clock speed of Basilisk from 33 MHz to 77 MHz and reduced the cell area from 1.8 MGE to 1.1 MGE, while also minimizing synthesis runtime and memory usage.

Place and Route (PnR) Enhancements

The PnR process using OpenROAD experienced several improvements:

• Optimized power grid design: Enabling better routing congestion management underneath power stripes.
• Routability enhancements: Adjusting physical implementation flow parameters to reduce DRC violations and improve core utilization.

These measures allowed Basilisk to achieve zero DRC violations, increased core area utilization by 10%, and decreased the overall die area by 12%, thus contributing to a more efficient and compact design.

Implications and Future Work

The successful tapeout of Basilisk presents several crucial implications for both OSHW and the broader electronics industry. The ability to produce a Linux-capable, fully auditable SoC using entirely open-source tools signifies a substantial stride towards greater transparency and security in hardware manufacturing. This accomplishment facilitates independent verification of hardware supply chains, enhancing trust and reliability in the deployed systems.

Future research directions are likely to focus on integrating secure cryptographic elements and root of trust (RoT) IPs to further consolidate the security framework of open-source SoCs. Additionally, continued enhancements to the open-source EDA toolchain and extending Basilisk’s capabilities with more advanced peripherals and multi-core configurations will be critical in driving the OSHW agenda forward.

The advancements detailed in this paper highlight the potential of open-source methodologies to produce high-performing, reliable, and secure silicon. Basillisk stands as a testament to what collaborative, transparent hardware development can achieve, heralding a more open future for the semiconductor industry.