Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design? (2405.04257v2)

Abstract: Designing complex, multi-million-gate application-specific integrated circuits requires robust and mature electronic design automation (EDA) tools. We describe our efforts in enhancing the open-source Yosys+Openroad EDA flow to implement Basilisk, a fully open-source, Linux-booting RV64GC system-on-chip (SoC) design. We analyze the quality-of-results impact of our enhancements to synthesis tools, interfaces between EDA tools, logic optimization scripts, and a newly open-sourced library of optimized arithmetic macro-operators. We also introduce a streamlined physical design flow with an improved power grid and cell placement integration. Our Basilisk SoC design was taped out in IHP's open 130 nm technology. It achieves an operating frequency of 77 MHz (51 logic levels) under typical conditions, a 2.3x improvement compared to the baseline open-source EDA flow, while also reducing logic area by 1.6x. Furthermore, tool runtime was reduced by 2.5x, and peak RAM usage decreased by 2.9x. Through collaboration with EDA tool developers and domain experts, Basilisk establishes solid "proof of existence" for a fully open-source EDA flow used in designing a competitive multi-million-gate digital SoC.

• The paper presents major synthesis optimizations to Yosys that reduce logic area by 39% and boost operating frequency by 2.3x compared to baseline flows.
• The paper integrates hand-optimized arithmetic units to refine datapath performance and shorten critical paths in the SoC design.
• The paper enhances place-and-route strategies to achieve zero design rule violations and a 77 MHz operating frequency on a 1.1M gate equivalent design.

Open-Source EDA for Multi-Million-Gate ASIC Design: Evaluation and Improvements

The paper "Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?" examines the capabilities of open-source Electronic Design Automation (EDA) tools in designing complex system-on-chip (SoC) architectures. The authors present their work on the Basilisk project, which showcases an RV64GC SoC capable of booting Linux, implemented entirely through open-source methodologies.

Major Contributions and Findings

Basilisk represents a significant implementation exercise using the Yosys+OpenROAD flow, aiming to measure and enhance the quality-of-results (QoR) for such open-source solutions compared to commercial EDA offerings. Key contributions from this work are as follows:

1. Synthesis Optimizations: The authors significantly optimize Yosys for better QoR. They address inefficiencies in part-select synthesis, overhaul internal ABC scripting utilizing Lazy Man’s Synthesis (LMS), and enhance it with new delay models. These adjustments lead to a notable reduction of logic area by 39% and a 2.3x improvement in the operating frequency compared to the base open-source flow.
2. Integration of Arithmetic Units: By integrating a library of hand-optimized arithmetic macro-operators, the QoR is further improved. The authors refined the synthesis of arithmetic operations with optimized implementations leading to a reduction in the critical path of essential datapath operations.
3. Place-and-Route Strategies: Enhancements to the OpenROAD flow scripts and the physical constraint configurations lead to reduced congestion and better routing solutions. The optimized process ends with zero design rule check (DRC) violations, marking a substantial validation of the approach.
4. Physical Design Flow: The researchers propose a streamlined flow with improved power grid and cell placement integration, achieving a core utilization of 55% with a synthesized logic area of 1.1 million gate equivalents, and an operational frequency boost to 77 MHz, underscoring both the feasibility and transferability of the openly available toolchain improvements.

Implications and Future Directions

Basilisk serves not only as proof of viability but also as a substantial enhancement to the capabilities of open-source EDA flows in handling large-scale, complex digital designs—designs typically dominated by proprietary toolchains. The systematic improvements in Yosys and OpenROAD, and their respective synthesis and place-and-route processes, indicate an upward trajectory for open-source EDA tool application in industry-critical contexts.

Moreover, the work under Basilisk signals potential pathways for further improvements in open source EDA, notably in tighter integration of optimization passes with backend-aware synthesis and more aggressive timing- and area-driven optimizations. Long-term, the developments could guide efforts to establish standardized interfaces and formats between synthesis and P&R tools to seamlessly integrate constraints, timing models, and optimization paths.

Despite achieving closer parity with commercial tools, there remains scope for improving the timing-aware synthesis, enhancing the library of pre-optimized blocks, and integrating backend insights into the synthesis flow to realize consistent QoR at even more advanced technology nodes.

Conclusion

The paper sets a formidable benchmark in extending the potential of open-source EDA tools, contributing critical insights and tools to the community. Open-source flows like Basilisk sanction access to sophisticated design methodologies at reduced cost and constraints, making them attractive alternatives or complements to proprietary EDA solutions. Continuing this trajectory could ensure open-source methodologies not only catch up to but strategically outpace traditional tools in certain application domains, especially in fostering collaboration, transparency, and innovation across silicon design processes.