Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization (2401.12205v1)

Abstract: Logic synthesis, a pivotal stage in chip design, entails optimizing chip specifications encoded in hardware description languages like Verilog into highly efficient implementations using Boolean logic gates. The process involves a sequential application of logic minimization heuristics (`synthesis recipe"), with their arrangement significantly impacting crucial metrics such as area and delay. Addressing the challenge posed by the broad spectrum of design complexities - from variations of past designs (e.g., adders and multipliers) to entirely novel configurations (e.g., innovative processor instructions) - requires a nuancedsynthesis recipe` guided by human expertise and intuition. This study conducts a thorough examination of learning and search techniques for logic synthesis, unearthing a surprising revelation: pre-trained agents, when confronted with entirely novel designs, may veer off course, detrimentally affecting the search trajectory. We present ABC-RL, a meticulously tuned $\alpha$ parameter that adeptly adjusts recommendations from pre-trained agents during the search process. Computed based on similarity scores through nearest neighbor retrieval from the training dataset, ABC-RL yields superior synthesis recipes tailored for a wide array of hardware designs. Our findings showcase substantial enhancements in the Quality-of-result (QoR) of synthesized circuits, boasting improvements of up to 24.8% compared to state-of-the-art techniques. Furthermore, ABC-RL achieves an impressive up to 9x reduction in runtime (iso-QoR) when compared to current state-of-the-art methodologies.

• The paper introduces ABC-RL, which integrates retrieval-guided reinforcement learning to dynamically select effective logic transformations.
• It employs a pre-trained agent to assess design novelty and guide the online synthesis process for optimized Boolean circuits.
• Empirical evaluations demonstrate a 24.8% improvement in the area-delay product compared to state-of-the-art methods.

Overview

Electronic Design Automation (EDA) lies at the heart of modern chip design processes, converting high-level descriptions into physical artifacts that can be fabricated. A crucial component of EDA is logic synthesis, where hardware description language (HDL) is translated into a Boolean gate-level network via logic optimization. This paper introduces ABC-RL, a retrieval-guided reinforcement learning (RL) approach to Boolean circuit minimization.

Logic Synthesis and Challenges

The authors articulate the intrinsic complexity of finding an optimal sequence of logic transformations, dubbed a "synthesis recipe," from the vast available space. While human expertise has traditionally played a central role in determining these sequences, the breadth of possible designs, from standardized components such as adders to custom architectures for novel processor instructions, motivates an automated solution. Existing RL methods in this space have either not utilized prior solutions optimally or have failed to generalize well for new designs.

Retrieval-Guided Reinforcement Learning

ABC-RL addresses this need by incorporating pre-trained agents within the RL framework, which help inform the online search process. A cornerstone of the proposed method is the use of a retrieval mechanism that ascertains how "innovative" a new netlist is by computing its similarity to prior designs. This similarity influences the decision-making of the ABC-RL, by adjusting a tuning factor, α, that determines the trust placed on the pre-trained RL agent. In essence, ABC-RL employs a hybrid approach, balancing between learned heuristics from past data and fresh exploration, proportionate to the novelty of the task at hand.

Core Contributions and Findings

The paper's empirical evaluations are comprehensive. They utilize a large dataset of hardware designs, which spans a wide array of design complexities. The authors find that ABC-RL surpasses state-of-the-art methodologies in terms of the quality of synthesized circuits, substantially reducing the runtime required to achieve comparable results. The evidence indicates that ABC-RL can yield a 24.8% geometric mean improvement in the area-delay product over existing methods, marking a significant advance in automated logic synthesis.

Conclusion

ABC-RL exemplifies a practical synergy of retrieval mechanisms and RL, applied to the domain of logic synthesis. The success of ABC-RL illustrates that a smart interplay between leveraging historical data and adapting to new challenges can resolve the complexities inherent in automated design processes. This work not only provides a significant step forward for the field of EDA but also posits a novel approach that may be of interest in other domains where online runtime is limited and distribution shifts between training and testing data are pivotal.