Acceptor-induced bulk dielectric loss in superconducting circuits on silicon (2402.17155v1)

Abstract: The performance of superconducting quantum circuits is primarily limited by dielectric loss due to interactions with two-level systems (TLS). State-of-the-art circuits with engineered material interfaces are approaching a limit where dielectric loss from bulk substrates plays an important role. However, a microscopic understanding of dielectric loss in crystalline substrates is still lacking. In this work, we show that boron acceptors in silicon constitute a strongly coupled TLS bath for superconducting circuits. We discuss how the electronic structure of boron acceptors leads to an effective TLS response in silicon. We sweep the boron concentration in silicon and demonstrate the bulk dielectric loss limit from boron acceptors. We show that boron-induced dielectric loss can be reduced in a magnetic field due to the spin-orbit structure of boron. This work provides the first detailed microscopic description of a TLS bath for superconducting circuits, and demonstrates the need for ultrahigh purity substrates for next-generation superconducting quantum processors.

• The paper identifies boron acceptors as a significant source of TLS-induced dielectric loss in superconducting circuits.
• The loss scales proportionally with boron concentration, highlighting the need for high-purity silicon substrates to enhance qubit coherence.
• Application of magnetic fields mitigates dielectric loss, offering a practical pathway for dynamic loss control in quantum devices.

Acceptor-Induced Bulk Dielectric Loss in Superconducting Circuits on Silicon

The paper "Acceptor-induced bulk dielectric loss in superconducting circuits on silicon" presents a comprehensive paper investigating the dielectric loss mechanisms in superconducting quantum circuits fabricated on silicon substrates. The major focus is the contribution of boron acceptors to two-level system (TLS) induced dielectric losses, which challenge the performance and coherence of quantum circuits. This work serves to augment the existing understanding of dielectric losses and identifies the significance of bulk crystalline defects in silicon, particularly boron acceptors, as a critical source of TLS noise that compromises qubit fidelity.

Key Findings

The pivotal findings of the paper are centered around the identification and mitigation of TLS-induced dielectric losses, secured through both experimental and theoretical analyses:

1. Boron Acceptors as TLS Sources: Through detailed analysis, the paper establishes that boron acceptors in silicon result in significant TLS activity. The two-level systems manifesting from these acceptors arise from their electronic structure and exhibit a strong coupling to the resonators' electric fields, making the dielectric loss substantial.
2. Impact of Boron Concentration: It is determined that the dielectric loss due to boron acceptors scales proportionally with boron concentration. This finding underscores the necessity for using ultra-high purity silicon substrates, with minimal boron concentration, to diminish the dielectric losses and enable the advancements needed for next-generation superconducting quantum processors.
3. Magnetic Field Mitigation of Loss: An intriguing aspect of this research is the effect of magnetic fields on dielectric losses. Application of magnetic fields can notably reduce boron-induced TLS losses, attributed to the alteration of the electronic structure under magnetic influence that effectively decouples the TLS from the resonant frequency of interest. This method presents itself as a useful strategy for controlling the losses in devices if high purity substrates are unattainable.
4. Design Implications: The analysis supports the trend towards surface treatment techniques and optimized circuit designs to alleviate dielectric losses not just from the surface but the bulk substrate as well. The role of increased bulk participation in energy necessitates new fabrication protocols to optimize qubit performance beyond the current focus on interface and surface effects.

Theoretical and Practical Implications

The findings laid out in this paper extend the theoretical comprehension of TLS mechanisms within silicon substrates and propose practical implications to improve the performance of superconducting circuits:

• Theoretical Modeling: The paper presents a nuanced view of the standard tunneling model applied to crystalline substrates, proposing that TLSs can have origins other than traditional interface imperfections. This widens the scope for theoretical models to include crystalline defects as significant contributors to quantum decoherence.
• Substrate Purity Specifications: Practically, the work highlights the pressing need for silicon wafers devoid of boron impurities to maintain low dielectric loss tangents that are crucial for qubit lifetime improvements. This insight is valuable for both material scientists working on semiconductor fabrication and the quantum computing community focusing on device architecture.
• Future Applications: The control over TLS-induced losses using magnetic fields introduces pathways for novel device designs where dielectric loss control can be dynamically adjusted, potentially leading to adaptive quantum systems and opening up new avenues for quantum computation hardware technologies.

Conclusion and Speculation for Future Development

In conclusion, the paper provides an in-depth exploration into how boron acceptors incite TLS-related losses in superconducting circuits on silicon. It both expands the foundational understanding of TLS effects in solid-state devices and offers tangible paths towards mitigating such losses through material purity and external field manipulation. Future developments are likely to probe further into the microscopic origins and potential control mechanisms for crystalline defects, advancing both material science and quantum information processing realms. Enhanced collaboration between these fields could lead to pioneering materials optimized for quantum coherence, meeting the ever-increasing demands for scalability and performance in quantum computing.