Papers
Topics
Authors
Recent
Gemini 2.5 Flash
Gemini 2.5 Flash
136 tokens/sec
GPT-4o
11 tokens/sec
Gemini 2.5 Pro Pro
47 tokens/sec
o3 Pro
5 tokens/sec
GPT-4.1 Pro
38 tokens/sec
DeepSeek R1 via Azure Pro
28 tokens/sec
2000 character limit reached

Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning (2312.14536v1)

Published 22 Dec 2023 in cs.AI and cs.AR

Abstract: Rewriting is a common procedure in logic synthesis aimed at improving the performance, power, and area (PPA) of circuits. The traditional reconvergence-driven And-Inverter Graph (AIG) rewriting method focuses solely on optimizing the reconvergence cone through Boolean algebra minimization. However, there exist opportunities to incorporate other node-rewriting algorithms that are better suited for specific cones. In this paper, we propose an adaptive reconvergence-driven AIG rewriting algorithm that combines two key techniques: multi-strategy-based AIG rewriting and strategy learning-based algorithm selection. The multi-strategy-based rewriting method expands upon the traditional approach by incorporating support for multi-node-rewriting algorithms, thus expanding the optimization space. Additionally, the strategy learning-based algorithm selection method determines the most suitable node-rewriting algorithm for a given cone. Experimental results demonstrate that our proposed method yields a significant average improvement of 5.567\% in size and 5.327\% in depth.

Definition Search Book Streamline Icon: https://streamlinehq.com
References (26)
  1. A. Mishchenko, S. Chatterjee, and R. Brayton, “DAG-aware AIG rewriting: a fresh look at combinational logic synthesis,” in ACM/IEEE Design Automation Conference, 2006, pp. 532–535.
  2. N. Li and E. Dubrova, “AIG rewriting using 5-input cuts,” in IEEE International Conference on Computer Design, 2011, pp. 429–430.
  3. H. Riener, A. Mishchenko, and M. Soeken, “Exact DAG-Aware Rewriting,” in IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition, 2020, pp. 732–737.
  4. A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, “Combinational and sequential mapping with priority cuts,” in IEEE/ACM International Conference on Computer-Aided Design, 2007.
  5. B. R. Alan Mishchenko, “Scalable logic synthesis using a simple circuit structure,” in Proc. IWLS, vol. 6, 2006, pp. 15–22.
  6. H. Riener, S.-Y. Lee, A. Mishchenko, and G. De Micheli, “Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis,” in 27th Asia and South Pacific Design Automation Conference, 2022, pp. 395–402.
  7. H. Riener, W. Haaswijk, and et al., “On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis,” in IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition, 2019, pp. 1649–1654.
  8. J. Zhang, L. Ni, and et al., “Enhanced Fast Boolean Matching Based on Sensitivity Signatures Pruning,” in IEEE/ACM International Conference On Computer Aided Design, 2021, p. 1–9.
  9. T. Sasao and J. Butler, “Worst and best irredundant sum-of-products expressions,” IEEE Transactions on Computers, vol. 50, no. 9, pp. 935–948, 2001.
  10. W. Haaswijk, M. Soeken, A. Mishchenko, and G. De Micheli, “SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 4, pp. 871–884, 2020.
  11. A. Mishchenko, R. Brayton, S. Jang, and V. Kravets, “Delay optimization using SOP balancing,” in IEEE/ACM International Conference on Computer-Aided Design, 2011, pp. 375–382.
  12. J. Vygen, “Slack in static timing analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 9, pp. 1876–1885, 2006.
  13. J. Cong, C. Wu, and Y. Ding, “Cut ranking and pruning: Enabling a general and efficient FPGA mapping solution,” in Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, 1999, pp. 29–35.
  14. K.-C. Chen and J.-Y. Yang, “Boolean matching algorithms,” in 1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers, 1993, pp. 44–48.
  15. W. Haaswijk, E. Collins, and et al., “Deep Learning for Logic Optimization Algorithms,” in IEEE International Symposium on Circuits and Systems, 2018, pp. 1–4.
  16. A. Hosny, S. Hashemi, M. Shalan, and S. Reda, “DRiLLS: Deep reinforcement learning for logic synthesis,” in ACM/IEEE Asia and South Pacific Design Automation Conference, 2020, pp. 581–586.
  17. C. Wang, C. Chen, D. Li, and B. Wang, “Rethinking Reinforcement Learning based Logic Synthesis,” 2022.
  18. A. Grosnit, C. Malherbe, and et al., “BOiLS: Bayesian Optimisation for Logic Synthesis,” in IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition, 2022, pp. 1193–1196.
  19. G. Pasandi, S. Pratty, and J. Forsyth, “AISYN: AI-driven Reinforcement Learning-Based Logic Synthesis Framework,” 2023, arXiv:2302.06415.
  20. G. Pasandi, S. Nazarian, and M. Pedram, “Approximate logic synthesis: A reinforcement learning-based technology mapping approach,” in IEEE International Symposium on Quality Electronic Design, 2019, pp. 26–32.
  21. C. J. Watkins and P. Dayan, “Q-learning,” Machine learning, vol. 8, pp. 279–292, 1992.
  22. F. S. Melo, “Convergence of Q-learning: A simple proof,” Institute Of Systems and Robotics, Tech. Rep, pp. 1–4, 2001.
  23. L. Amarú, P.-E. Gaillardon, and G. De Micheli, “The EPFL combinational benchmark suite,” in 24th International Workshop on Logic & Synthesis, no. CONF, 2015.
  24. Berkeley Logic Synthesis and Verification Group, “ABC: A System for Sequential Synthesis and Verification,” https://people.eecs.berkeley.edu/ alanmi/abc/.
  25. S. Pal and S. Mitra, “Multilayer perceptron, fuzzy sets, and classification,” IEEE Transactions on Neural Networks, vol. 3, no. 5, pp. 683–697, 1992.
  26. M. Soeken, H. Riener, and et al., “The EPFL logic synthesis libraries,” Jun. 2022, arXiv:1805.05121v3.
Citations (3)

Summary

We haven't generated a summary for this paper yet.