Topology-Aware Modeling (TAM) Framework

Updated 3 July 2025

Topology-Aware Modeling (TAM) Framework is an approach that integrates SOC scan-chain topology with resource allocation using geometric rectangle packing to minimize test time.
It balances core-level scan chains and global architectural constraints to ensure efficient TAM utilization and reduce test scheduling idle times.
The methodology involves generating wrapper configurations, sorting according to a diagonal metric, and dynamically scheduling cores based on available TAM resources.

The Topology-Aware Modeling (TAM) Framework in system-on-chip (SOC) testing refers to a class of algorithmic approaches designed to efficiently co-optimize test wrapper construction and Test Access Mechanism (TAM) resource allocation, with direct consideration of the structural and resource topology of the chip. In the context of “Efficient Wrapper/TAM Co-Optimization for SOC Using Rectangle Packing”, TAM denotes both the explicit integration of core-level scan network topology and the global architectural constraints of the SOC to minimize test application time through geometric algorithmic strategies.

1. Principles of Wrapper/TAM Co-Optimization

SOC testing involves delivering test data to multiple embedded cores through TAM wires, where each core is surrounded by a wrapper (a network of scan-chains and wrapper cells) interfacing it to the TAM. The test time for an SOC is strongly influenced by both the design of these wrappers and the schedule by which TAM resources are assigned to cores.

The central TAM principle is the joint optimization of wrapper and TAM: rather than treating these aspects independently, the method seeks globally minimal test application time by considering the interaction between core scan structure, available TAM width, and allocation order. This is accomplished by mapping the scheduling problem to a geometric “rectangle packing” model, which holistically accounts for the overlapping resource demands of SOC cores.

Wrapper design aims to balance scan-chains so that the length of the longest chain (which dominates core test time), $\max\{s_i, s_o\}$ , is minimized, as quantified by: $T_{core} = p \times [1 + \max\{s_i, s_o\}] + \min\{s_i, s_o\}$ where $p$ is the number of test vectors, and $s_i$ , $s_o$ are input/output scan cycles.

2. Rectangle Packing Model and Scheduling Algorithm

The TAM framework encodes each core’s wrapper/TAM/test configuration as a rectangle:

Rectangle height: TAM width assigned to the core ( $H_i$ )
Rectangle width: result test time under that TAM width ( $W_i$ )
The “bin” to pack into: height $W_{max}$ (full SOC-wide TAM width), width is the time axis

The problem is thus to “pack” each core’s corresponding rectangle in the bin without horizontal overlap (no exceeding $W_{max}$ wires at any time), such that the total SOC test time (bin width) is minimized.

The framework forbids rectangle splitting—that is, a core’s test must be executed contiguously and cannot share TAM wires with another core at the same time.

Scheduling proceeds by:

Generating, for each core, a set of possible rectangles (for various feasible TAM assignments)
Sorting these rectangles—not solely by width (test time), but by a diagonal length metric:

$DL_i = \sqrt{H_i^2 + (W_i/T_{min})^2}$

where $T_{min}$ is the minimal achievable test time across all cores.

Packing (scheduling) in descending $DL$ order, assigning to available TAM wires as possible, and reducing TAM assignment or pending the core if not enough wires are available.

This diagonal length criterion ensures that both bandwidth-hungry and time-hungry cores are prioritized, achieving better global resource utilization compared to width-only sorting.

3. Topology Awareness and Integration

The term "topology-aware" in this context refers to the explicit modeling, at runtime, of both the core-internal scan-chain architecture and the SOC's global resource sharing structure:

Wrapper construction takes into account the number and arrangement of scan-chains and I/Os for each core, aiming for balanced partitions under current TAM availability.
Scheduling/packing directly models mutual exclusion of TAM wires: cores cannot share wires at the same time, and the assignment evolves dynamically with current schedule status.
The packing strategy, the wrapper scan-chain balancing, and the order of resource allocation are sensitive to core-level and system-level topological constraints.

This approach enables the framework to navigate around resource-contention hot-spots and to minimize idle time, as opposed to static or fixed-width resource assignment methods.

4. Implementation Methodology and Algorithms

Implementation of this TAM framework involves the following main steps:

Wrapper Design:
- For each core, determine the scan chain structure and I/O assignment.
- For combinational cores, if $I+O \leq W_{max}$ , assign one TAM wire per I/O; otherwise, construct $W_{max}$ wrapper chains.
- For sequential cores, compute the upper bound on scan elements per wrapper chain,” assign internal scan chains greedily to balance chain lengths, and then map functional I/Os for further balance.
- The precise method is given as pseudocode in the source, typically following a sort-and-greedy assignment protocol.
Rectangle Construction for Scheduling:
- For each wrapper configuration, enumerate rectangles for feasible TAM assignments.
- For every rectangle, record paired values (TAM width, test time).
Rectangle Sorting and Scheduling:
- Normalize all rectangle widths by $T_{min}$ .
- Compute and sort rectangles by diagonal length.
- Iteratively schedule cores, allocating maximal TAM width available at each scheduling step, falling back to reduced widths if necessary, and queueing unschedulable jobs.
Resource and Schedule Updates:
- As cores complete testing, update available TAM wires and schedule pending jobs accordingly.

5. Implications for SOC Design and Testing

Employing this topology-aware rectangle packing approach leads to:

Reduced overall test time, as resource allocation adapts flexibly to current demand, avoiding both underutilization and bottlenecking.
Improved TAM utilization efficiency, as the framework balances loading across available TAM wires and minimizes idle resource slices.
Better scalability: The method is appropriate for large SOCs with numerous, heterogeneous cores, due to its modularity and sensitivity to core-specific constraints.
Operational flexibility: The technique can readily incorporate additional constraints, such as test power limits or physical design constraints, with modest algorithmic extensions.

6. Key Mathematical Formulations

Some of the principal formulas supporting this framework include:

Core Test Time:

$T_{core} = p \times [1 + \max\{s_i, s_o\}] + \min\{s_i, s_o\}$

Peak Scan Element Constraint (for wrapper chain balancing):

$Peak\_Scan\_Element = \frac{Total\_Scan\_Element}{W_{max}/2}$

Diagonal Length for Scheduling Order:

$DL_i = \sqrt{H_i^2 + \left( \frac{W_i}{T_{min}} \right)^2 }$

7. Summary of Co-Optimization Steps

Step	Description
1	Design wrappers for each core given available TAM width
2	Enumerate rectangle (TAM width, test time) pairs per core
3	Normalize widths and compute diagonal lengths for each rectangle
4	Sort cores by descending diagonal length
5	Iteratively pack rectangles, respecting TAM constraints
6	Update available TAMs and repeat until all cores scheduled

8. Broader Context and Outlook

The SOC TAM framework exemplified here is a foundation for advanced test resource management. Its core insight—connecting physical scan/IO structure to a geometric, “topology-aware” optimization—has influenced subsequent resource-constrained scheduling methods, and it readily adapts to industrial CAD flows. A plausible implication is that related geometric packing and constraint-based scheduling strategies could be deployed in other domains of concurrent resource management, such as embedded system multi-core deployment or network-on-chip bandwidth allocation.

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