Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration (2506.15440v1)

Abstract: Developing accurate and reliable Compute-In-Memory (CIM) architectures is becoming a key research focus to accelerate AI tasks on hardware, particularly Deep Neural Networks (DNNs). In that regard, there has been significant interest in analog and mixed-signal CIM architectures aimed at increasing the efficiency of data storage and computation to handle the massive amount of data needed by DNNs. Specifically, resistive mixed-signal CIM cores are pushed by recent progresses in emerging Non-Volatile Memory (eNVM) solutions. Yet, mixed-signal CIM computing cores still face several integration and reliability challenges that hinder their large-scale adoption into end-to-end AI computing systems. In terms of integration, resistive and eNVM-based CIM cores need to be integrated with a control processor to realize end-to-end AI acceleration. Moreover, SRAM-based CIM architectures are still more efficient and easier to program than their eNVM counterparts. In terms of reliability, analog circuits are more susceptible to variations, leading to computation errors and degraded accuracy. This work addresses these two challenges by proposing a self-calibrated mixed-signal CIM accelerator SoC, fabricated in 22-nm FDSOI technology. The integration is facilitated by (1) the CIM architecture, combining the density and ease of SRAM-based weight storage with multi-bit computation using linear resistors, and (2) an open-source programming and testing strategy for CIM systems. The accuracy and reliability are enabled through an automated RISC-V controlled on-chip calibration, allowing us to improve the compute SNR by 25 to 45% across multiple columns to reach 18-24 dB. To showcase further integration possibilities, we show how our proof-of-concept SoC can be extended to recent high-density linear resistor technologies for enhanced computing performance.

• The paper introduces a self-calibration mechanism using RISC-V that improves compute SNR by 25-45% in mixed-signal CIM cores.
• It implements a CIM core architecture combining SRAM-based weight storage with multi-bit linear resistor computation to enhance AI acceleration.
• The open-source framework facilitates integration and testing in AI systems while addressing reliability challenges in analog computing.

Acore-CIM: An Advanced Approach for Mixed-Signal CIM Architectures with Self-Calibration

The paper "Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration" presents a significant advancement in the development of Compute-In-Memory (CIM) architectures, particularly those aimed at accelerating AI tasks. The paper focuses on addressing the key integration and reliability challenges associated with mixed-signal CIM cores, utilizing a RISC-V controlled self-calibration strategy.

Overview of Acore-CIM’s Contributions

The research specifically discusses the challenges associated with resistive mixed-signal CIM cores. The integration of CIM cores with a control processor and ensuring computational reliability are crucial for the widespread adoption of CIM architectures in end-to-end AI systems. Acore-CIM tackles these challenges by leveraging a self-calibrated mixed-signal CIM accelerator System-on-Chip (SoC), implemented in 22-nm Fully Depleted Silicon On Insulator (FDSOI) technology.

Key contributions of the paper include:

1. CIM Core Architecture: The architecture focuses on the combination of SRAM-based weight storage with multi-bit computation through linear resistors, facilitating the integration of emerging Non-Volatile Memory (eNVM) solutions. This approach improves computational density while maintaining ease of programming.
2. Open-Source System Framework: The Acore-CIM framework is designed to facilitate integration in complete AI systems using RISC-V processors. The authors provide a comprehensive open-source programming and testing strategy, enabling enhanced system flexibility and testing efficiency.
3. Self-Calibration Mechanism: Acore-CIM introduces a RISC-V controlled Built-In Self-Calibration (BISC) routine that automatically adjusts gain and offset errors. This calibration improves the compute Signal-to-Noise Ratio (SNR) by 25 to 45%, achieving a range of 18-24 dB, thus ensuring high computational accuracy across all CIM columns.
4. Integration with High-Density Linear Resistor Technologies: The paper outlines potential expansion compatibility with High-Density Linear Resistor (HDLR) technologies, which promise denser implementation and improved power efficiency for CIM cores.

Implications and Future Scope

The implications of this research are notable for both practical and theoretical developments in mixed-signal CIM architectures:

• Practical Implications: The integration of mixed-signal CIM cores with self-calibration capabilities significantly enhances their reliability, particularly in resource-intensive AI applications such as Deep Neural Networks (DNNs). The self-calibration approach minimizes the need for manual adjustments, reducing overhead and improving the scalability of these systems in real-world applications.
• Theoretical Advances: This paper advances the theoretical understanding of CIM core integration and calibration, providing a robust framework for addressing analog non-idealities and variability challenges. The RISC-V based control and calibration system offers a template for future AI accelerators necessitating high accuracy.
• Future Developments: The proof-of-concept implementation sets the stage for further research into advanced CIM core designs, potentially integrating even more efficient memory technologies. Future work could explore scalability to larger arrays and varied analog computing technologies, further optimizing the balance between computational efficiency and energy consumption.

In conclusion, the Acore-CIM paper provides a comprehensive examination of a self-calibrating mixed-signal CIM architecture, offering a blend of enhanced computational reliability and integration strategies within AI accelerators. This paper represents a critical step toward realizing efficient, scalable CIM solutions for next-generation AI applications.