Roadmap to fault tolerant quantum computation using topological qubit arrays (2502.12252v2)

Abstract: We describe a concrete device roadmap towards a fault-tolerant quantum computing architecture based on noise-resilient, topologically protected Majorana-based qubits. Our roadmap encompasses four generations of devices: a single-qubit device that enables a measurement-based qubit benchmarking protocol; a two-qubit device that uses measurement-based braiding to perform single-qubit Clifford operations; an eight-qubit device that can be used to show an improvement of a two-qubit operation when performed on logical qubits rather than directly on physical qubits; and a topological qubit array supporting lattice surgery demonstrations on two logical qubits. Devices that enable this path require a superconductor-semiconductor heterostructure that supports a topological phase, quantum dots and coupling between those quantum dots that can create the appropriate loops for interferometric measurements, and a microwave readout system that can perform fast, low-error single-shot measurements. We describe the key design components of these qubit devices, along with the associated protocols for demonstrations of single-qubit benchmarking, Clifford gate execution, quantum error detection, and quantum error correction, which differ greatly from those in more conventional qubits. Finally, we comment on implications and advantages of this architecture for utility-scale quantum computation.

Roadmap to Fault-Tolerant Quantum Computation Using Topological Qubit Arrays

This paper outlines a development plan for achieving fault-tolerant quantum computation using Majorana-based qubits, focusing on their topological protection properties. Majorana zero modes (MZMs) serve as the backbone for constructing noise-resistant qubits by leveraging the topological nature of these platforms. The research outlines a multi-step roadmap divided into four major phases, each building on the advancements and knowledge gained from previous steps.

Device Generations and Key Milestones

1. Single-Qubit Device: Measurement-Based Benchmarking The roadmap starts with the development of a single-qubit device based on tetrons—qubits consisting of four Majorana zero modes. This configuration enables measurement-based benchmarking, a protocol devised to evaluate the qubit's properties by performing non-commuting Pauli measurements (specifically $X$ and $Z$). The proposed metrics for assessing these measurements—the operational assignment error and operational bias—allow researchers to quantify deviations from perfect projective measurements using sequences of Pauli measurements.
2. Two-Qubit Device: Measurement-Based Braiding The second phase introduces a two-qubit device that supports single- and two-qubit operations, allowing for complete Clifford operations by using measurement-based braiding transformations. This phase emphasizes the advantages of measurement-only topological quantum computation, wherein unitary operations are replaced by specific sequences of measurements without physically moving MZMs.
3. Eight-Qubit Device: Quantum Error Detection The third phase focuses on quantum error detection using an eight-qubit arrangement. This configuration aims to demonstrate the benefits of topological protection by outperforming operations on logical qubits compared to physical qubits. A significant hurdle addressed here is the need for repeated error correction cycles, pivotal for maintaining logical qubit fidelity on par with or better than physical qubits.
4. Topological Qubit Array for Lattice Surgery The final stage outlines constructing larger systems capable of demonstrating lattice surgery, an essential feature enabling fault-tolerant logical operations between code patches. Specifically, this involves arrays of tetrons aligned to perform large-scale error correction efficiently. The architecture uniquely suits quadratic codes, such as Hastings-Haah codes, and surface codes relying on one- and two-qubit measurements, reinforcing this roadmap's relevance to scalable quantum computing initiatives.

Technical Considerations and Error Models

The paper also explores critical design elements, such as the choice between detuning-based and cutter-based control methods for initializing and measuring qubit states. These methodologies influence qubit coherence times and the efficacy of measurement-based operations. Additionally, an effective error model is proposed, accounting for assignment errors, single-qubit, and two-qubit Pauli errors, with specific emphasis on the latter's reduction through topological gap protection and enhancing signal-to-noise ratios.

Implications and Future Directions

The roadmap's broader implications suggest potential for development towards utility-scale quantum computation by ensuring physical qubits maintain error rates below the surface code threshold. The described architectural approach promises scalability largely due to its ability to reduce many error mechanisms exponentially through well-considered device and material engineering. Added flexibility in error detection and robust protocols for measurement-based quantum operations bolster the plan's feasibility against the challenges of existing superconducting qubit technologies.

This work posits a paradigm shift towards realizing a fault-tolerant quantum computer, promising an exciting avenue for future developments in quantum technology. The emphasis on practical, incremental improvements paves the way for laboratory demonstrations that align closely with theoretical performance predictions, thereby expediting the progress towards fully realizing quantum advantage in practical applications.