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The Emergence of Hardware Fuzzing: A Critical Review of its Significance (2403.12812v1)

Published 19 Mar 2024 in cs.CR

Abstract: In recent years, there has been a notable surge in attention towards hardware security, driven by the increasing complexity and integration of processors, SoCs, and third-party IPs aimed at delivering advanced solutions. However, this complexity also introduces vulnerabilities and bugs into hardware systems, necessitating early detection during the IC design cycle to uphold system integrity and mitigate re-engineering costs. While the Design Verification (DV) community employs dynamic and formal verification strategies, they encounter challenges such as scalability for intricate designs and significant human intervention, leading to prolonged verification durations. As an alternative approach, hardware fuzzing, inspired by software testing methodologies, has gained prominence for its efficacy in identifying bugs within complex hardware designs. Despite the introduction of various hardware fuzzing techniques, obstacles such as inefficient conversion of hardware modules into software models impede their effectiveness. This Systematization of Knowledge (SoK) initiative delves into the fundamental principles of existing hardware fuzzing, methodologies, and their applicability across diverse hardware designs. Additionally, it evaluates factors such as the utilization of golden reference models (GRMs), coverage metrics, and toolchains to gauge their potential for broader adoption, akin to traditional formal verification methods. Furthermore, this work examines the reliability of existing hardware fuzzing techniques in identifying vulnerabilities and identifies research gaps for future advancements in design verification techniques.

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References (126)
  1. J. C. Chen, H. Rau, C.-J. Sun, H.-W. Stzeng, and C.-H. Chen, “Workflow design and management for IC supply chain,” in International Conference on Networking, Sensing and Control, 2009, pp. 697–701.
  2. A.Yeh, “Trends in the global IC design service market,” last accessed : 11/19/2023. [Online]. Available: https://www.digitimes.com/news/a20120313RS400.html&chid=2
  3. TechInsights, “Apple iPhone 15 Pro Teardown,” last accessed 11/19/2023. [Online]. Available: https://www.techinsights.com/blog/apple-iphone-15-pro-teardown
  4. N. Artenstein, “Broadpwn: Remotely compromising android and iOS via a bug in broadcom’s Wi-Fi chipsets,” in BlackHat USA, 2017.
  5. Y. Liu, Y. Jin, A. Nosratinia, and Y. Makris, “Silicon demonstration of hardware trojan design and detection in wireless cryptographic ICs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, pp. 1506–1519, 2017.
  6. M. Lipp, M. Schwarz, D. Gruss, T. Prescher, W. Haas, A. Fogh, J. Horn, S. Mangard, P. Kocher, D. Genkin, Y. Yarom, and M. Hamburg, “Meltdown: Reading kernel memory from user space,” in USENIX Security Symposium, 2018.
  7. P. Kocher, J. Horn, A. Fogh, , D. Genkin, D. Gruss, W. Haas, M. Hamburg, M. Lipp, S. Mangard, T. Prescher, M. Schwarz, and Y. Yarom, “Spectre attacks: Exploiting speculative execution,” in IEEE Symposium on Security and Privacy (S&P’19), 2019.
  8. N. N. V. Database, last accessed 11/19/2023. [Online]. Available: https://nvd.nist.gov/
  9. REDSCAN, “2021 has officially been a record-breaking year for vulnerabilities.” last accessed 11/19/2023. [Online]. Available: https://www.redscan.com/news/nist-nvd-analysis-2021-record-vulnerabilities/#:~:text=2021%20was%20an%20especially%20difficult,50%20CVEs%20logged%20each%20day
  10. MITRE, “Cve database,” last accessed 11/19/2023. [Online]. Available: https://cveform.mitre.org/
  11. S. Engineering, “A glossary for chip and semiconductor ip security and trust,” last accessed 11/19/2023. [Online]. Available: https://semiengineering.com/a-glossary-for-chip-and-semiconductor-ip-security-and-trust/
  12. J. V. Bulck, M. Minkin, O. Weisse, D. Genkin, B. Kasikci, F. Piessens, M. Silberstein, T. F. Wenisch, Y. Yarom, and R. Strackx, “Foreshadow: Extracting the keys to the intel SGX kingdom with transient Out-of-Order execution,” in USENIX Security Symposium, 2018.
  13. M. Schwarz, M. Lipp, D. Moghimi, J. Van Bulck, J. Stecklina, T. Prescher, and D. Gruss, “Zombieload: Cross-privilege-boundary data sampling,” in ACM SIGSAC Conference on Computer and Communications Security, 2019.
  14. Y. Jang, S. Lee, and T. Kim, “Breaking kernel address space layout randomization with intel TSX,” in ACM SIGSAC Conference on Computer and Communications Security, 2016.
  15. R. Wojtczuk, “Xen security advisory 7 (CVE-2012-0217) - PV privilege escalation,” last accessed: 11/18/2023. [Online]. Available: https://lists.xen.org/archives/html/xen-announce/2012-06/msg00001.html
  16. T. Feng, H. Pei, Z. Jin, and X. Wu, “A survey and perspective on electronic design automation tools for ensuring soc security,” in International SoC Design Conference (ISOCC), 2022.
  17. P. Ghosh, V. N. Dwaraka Mai, A. Chopra, and B. Sood, “Self-checking performance verification methodology for complex SoCs,” in International Symposium on Quality Electronic Design (ISQED), 2023.
  18. K. Kang, S. Park, B. Bae, J. Choi, S. Lee, B. Lee, and J.-B. Lee, “Seamless SoC verification using virtual platforms: An industrial case study,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019.
  19. K. Alatoun, B. Shankaranarayanan, S. M. Achyutha, and R. Vemuri, “SoC trust validation using assertion-based security monitors,” in International Symposium on Quality Electronic Design (ISQED), 2021.
  20. S. Tang, X. Wang, Y. Gao, and W. Hu, “Accelerating SoC security verification and vulnerability detection through symbolic execution,” in International SoC Design Conference (ISOCC), 2022.
  21. P. Mohandoss and A. Rengaraj, “Pre-silicon DFT verification on SoC slim model,” in International Workshop on Microprocessor and SOC Test and Verification (MTV), 2018.
  22. S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-w teraFLOPS processor in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 29–41, 2008.
  23. R. Saravanan, S. Bavikadi, S. Rai, A. Kumar, and S. M. Pudukotai Dinakarrao, “Reconfigurable fet approximate computing-based accelerator for deep learning applications,” in 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, pp. 1–5.
  24. Intel, “Machine check error avoidance on page size change/CVE-2018-12207,” 2019, last accessed: 11/18/2023. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/troubleshooting/software-security-guidance/advisory-guidance/machine-check-error-avoidance-page-size-change.html
  25. MITRE, “Common weakness enumeration,” last accessed: 11/18/2023. [Online]. Available: https://cwe.mitre.org/data/index.html
  26. M. Chen and P. Mishra, “Property learning techniques for efficient generation of directed tests,” IEEE Transactions on Computers, vol. 60, no. 6, pp. 852–864, Feb 2011.
  27. R. Mukherjee, D. Kroening, and T. Melham, “Hardware verification using software analyzers,” in IEEE Computer Society Annual Symposium on VLSI, 2015.
  28. G. Dessouky, D. Gens, P. Haney, G. Persyn, A. Kanuparthi, H. Khattri, J. M. Fung, A.-R. Sadeghi, and J. Rajendran, “Hardfails: Insights into software-exploitable hardware bugs,” in USENIX Conference on Security Symposium, 2019.
  29. S. R. Sarangi, A. Tiwari, and J. Torrellas, “Phoenix: Detecting and recovering from permanent processor design bugs with programmable hardware,” in IEEE/ACM International Symposium on Microarchitecture, 2006.
  30. I. Wagner and V. Bertacco, “Engineering trust with semantic guardians,” in Design, Automation & Test in Europe Conference & Exhibition, 2007.
  31. J. Yang and A. Puder, “Tightly integrate dynamic verification with formal verification: a GSTE based approach,” in Asia and South Pacific Design Automation Conference, 2005.
  32. S. Gogri, A. Tyagi, M. Quinn, and J. Hu, “Transaction level stimulus optimization in functional verification using machine learning predictors,” in International Symposium on Quality Electronic Design (ISQED), 2022.
  33. O. Guzey, L.-C. Wang, J. R. Levitt, and H. Foster, “Increasing the efficiency of simulation-based functional verification through unsupervised support vector analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 1, pp. 138–148, 2010.
  34. S. Kasarapu, S. Shukla, and S. M. Pudukotai Dinakarrao, “Resource- and workload-aware model parallelism-inspired novel malware detection for iot devices,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 12, pp. 4618–4628, 2023.
  35. S. Kasarapu, S. Shukla, R. Hassan, A. Sasan, H. Homayoun, and S. M. PD, “Cad-fsl: Code-aware data generation based few-shot learning for efficient malware detection,” in Proceedings of the Great Lakes Symposium on VLSI 2022, ser. GLSVLSI ’22, 2022, p. 507–512.
  36. Cadence, “Cadence webpage,” last accessed: 11/20/2023. [Online]. Available: https://www.cadence.com/en_US/home.html
  37. ——, “Jaspergold formal verification platform,” last accessed: 11/18/2023. [Online]. Available: https://www.cadence.com/enUS/home/tools/system-design-and-verification/formal-and-static-verification/jasper-gold-verification-platform.html
  38. Siemens, “Questa advanced verification,” last accessed: 11/18/2023. [Online]. Available: https://eda.sw.siemens.com/en-US/ic/questa/
  39. Cadence, “Fastest simulator to achieve verification closure for IP and SoC designs,” last accessed: 11/20/2023. [Online]. Available: https://www.cadence.com/en_US/home/tools/system-design-and-verification/simulation-and-testbench-verification/xcelium-simulator.html
  40. Aldec, “Riviera-PRO: Advanced Verification Platform,” last accessed: 11/20/2023. [Online]. Available: https://www.aldec.com/en/products/functional_verification/riviera-pro
  41. Yosys, “Symbiyosys documentation,” last accessed: 11/18/2023. [Online]. Available: https://symbiyosys.readthedocs.io/en/latest/
  42. U. of California Berkley, “ABC,” last accessed: 11/20/2023. [Online]. Available: https://people.eecs.berkeley.edu/~alanmi/abc/
  43. S. Fine and A. Ziv, “Coverage directed test generation for functional verification using bayesian networks,” in Design Automation Conference, 2003.
  44. A. Olofsson, “Intelligent design of electronic assets (idea) & posh open source hardware (posh),” last accessed: 11/18/2023. [Online]. Available: https://www.darpa.mil/attachments/eri_design_proposers_day.pdf
  45. M. Hicks, C. Sturton, S. T. King, and J. M. Smith, “SPECS: A lightweight runtime mechanism for protecting software from security-critical processor bugs,” SIGPLAN Not., vol. 50, no. 4, p. 517–529, Mar 2015.
  46. Averant, “Averant solidify,” last accessed: 11/20/2023. [Online]. Available: http://www.averant.com/storage/documents/Solidify.pdf
  47. Onespin, “Onespin website,” last accessed: 11/18/2023. [Online]. Available: https://www.onespin.com/
  48. Synopsys, “Synopsys webpage,” last accessed: 11/18/2023. [Online]. Available: https://www.synopsys.com/
  49. Siemens, “Modelsim,” last accessed: 11/18/2023. [Online]. Available: https://eda.sw.siemens.com/en-US/ic/modelsim/
  50. P. D. Sai Manoj, H. Yu, C. Gu, and C. Zhuo, “A zonotoped macromodeling for reachability verification of eye-diagram in high-speed i/o links with jitter,” in 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2014, pp. 696–701.
  51. L. Ni, S. Manoj P. D., Y. Song, C. Gu, and H. Yu, “A zonotoped macromodeling for eye-diagram verification of high-speed i/o links with jitter and parameter variations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 6, pp. 1040–1051, 2016.
  52. Synopsys, “VCS: The industry’s highest performance simulation solutions,” last accessed: 11/18/2023. [Online]. Available: https://www.synopsys.com/verification/simulation/vcs.html
  53. F. Wang, H. Zhu, P. Popli, Y. Xiao, P. Bodgan, and S. Nazarian, “Accelerating coverage directed test generation for functional verification: A neural network-based framework,” in Great Lakes Symposium on VLSI, 2018.
  54. M. Tiwari, J. K. Oberg, X. Li, J. Valamehr, T. Levin, B. Hardekopf, R. Kastner, F. T. Chong, and T. Sherwood, “Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security,” in International Symposium on Computer Architecture (ISCA), 2011.
  55. A. Ardeshiricham, W. Hu, J. Marxen, and R. Kastner, “Register transfer level information flow tracking for provably secure hardware design,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.
  56. X. Li, M. Tiwari, J. K. Oberg, V. Kashyap, F. T. Chong, T. Sherwood, and B. Hardekopf, “Caisson: A hardware description language for secure information flow,” SIGPLAN Not., vol. 46, no. 6, p. 109–120, June 2011.
  57. X. Li, V. Kashyap, J. K. Oberg, M. Tiwari, V. R. Rajarathinam, R. Kastner, T. Sherwood, B. Hardekopf, and F. T. Chong, “Sapper: A language for hardware-level security policy enforcement,” in International Conference on Architectural Support for Programming Languages and Operating Systems, 2014.
  58. D. Zhang, Y. Wang, G. E. Suh, and A. C. Myers, “A hardware design language for timing-sensitive information-flow security,” in International Conference on Architectural Support for Programming Languages and Operating Systems, 2015.
  59. X. Meng, S. Kundu, A. K. Kanuparthi, and K. Basu, “RTL-contest: Concolic testing on RTL for detecting security vulnerabilities,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 3, pp. 466–477, 2022.
  60. T. Trippel, K. G. Shin, A. Chernyakhovsky, G. Kelly, D. Rizzo, and M. Hicks, “Fuzzing hardware like software,” in USENIX Security Symposium (USENIX Security), 2022.
  61. S. K. Muduli, G. Takhar, and P. Subramanyan, “Hyperfuzzing for SoC security validation,” in IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020.
  62. N. Kabylkas, T. Thorn, S. Srinath, P. Xekalakis, and J. Renau, “Effective processor verification with logic fuzzer enhanced co-simulation,” in IEEE/ACM International Symposium on Microarchitecture, 2021.
  63. R. Kande, A. Crump, G. Persyn, P. Jauernig, A.-R. Sadeghi, A. Tyagi, and J. Rajendran, “TheHuzz: Instruction fuzzing of processors using Golden-Reference models for finding Software-Exploitable vulnerabilities,” in USENIX Security Symposium (USENIX Security), 2022.
  64. S. Canakci, C. Rajapaksha, L. Delshadtehrani, A. Nataraja, M. Taylor, M. Egele, and A. Joshi, “Processorfuzz: Processor fuzzing with control and status registers guidance,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2023.
  65. X. Qin and P. Mishra, “Scalable test generation by interleaving concrete and symbolic execution,” in International Conference on VLSI Design, 2014.
  66. M. M. Hossain, A. Vafaei, K. Z. Azar, F. Rahman, F. Farahmandi, and M. Tehranipoor, “SoCFuzzer: SoC vulnerability detection using cost function enabled fuzz testing,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023.
  67. K. Laeufer, J. Koenig, D. Kim, J. Bachrach, and K. Sen, “RFUZZ: Coverage-directed fuzz testing of rtl on fpgas,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018.
  68. T. Li, H. Zou, L. D, and Q. W, “Symbolic simulation enhanced coverage-directed fuzz testing of RTL design,” in IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
  69. J. Hur, S. Song, D. Kwon, E. Baek, J. Kim, and B. Lee, “DifuzzRTL: Differential fuzz testing to find CPU bugs,” in IEEE Symposium on Security and Privacy (SP), 2021.
  70. K. Serebryany, “OSS-Fuzz - google’s continuous fuzzing service for open source software,” in USENIX Security Symposium, 2017.
  71. Microsoft, “Microsoft security risk detection,” last accessed 11/19/2023. [Online]. Available: https://www.microsoft.com/en-us/research/project/project-springfield/
  72. Google, “Americal fuzzy loop,” last accessed: 11/20/2023. [Online]. Available: https://github.com/google/AFL
  73. E. Bounimova, P. Godefroid, and D. Molnar, “Billions and billions of constraints: Whitebox fuzz testing in production,” in International Conference on Software Engineering (ICSE), 2013.
  74. S. Nagy and M. Hicks, “Full-speed fuzzing: Reducing fuzzing overhead through coverage-guided tracing,” in IEEE Symposium on Security and Privacy (SP), 2019.
  75. Kitplot, “Dharma - a generation-based, context-free grammar fuzzer,” last accessed: 11/18/2023. [Online]. Available: https://www.kitploit.com/2015/07/dharma-generation-based-context-free.html
  76. R.-V. W. Group, “Risc-v,” last accessed: 11/18/2023. [Online]. Available: https://riscv.org/
  77. O. W. Group, “Openrisc,” last accessed: 11/18/2023. [Online]. Available: https://openrisc.io/
  78. lowRISC, “Ibex,” last accessed 11/19/2023. [Online]. Available: https://lowrisc.org/
  79. Google, “Opentitan,” last accessed 11/19/2023. [Online]. Available: https://opentitan.org/
  80. X. Guo, R. G. Dutta, P. Mishra, and Y. Jin, “Automatic code converter enhanced pch framework for soc trust verification,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 12, pp. 3390–3400, 2017.
  81. X. Guo, R. G. Dutta, J. He, and Y. Jin, “Pch framework for ip runtime security verification,” in 2017 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2017, pp. 79–84.
  82. X. Guo, R. G. Dutta, and Y. Jin, “Eliminating the hardware-software boundary: A proof-carrying approach for trust evaluation on computer systems,” IEEE Transactions on Information Forensics and Security, vol. 12, no. 2, pp. 405–417, 2017.
  83. F. Farahmandi, Y. Huang, and P. Mishra, “Trojan localization using symbolic algebra,” in 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 2017, pp. 591–597.
  84. A. Biere, A. Cimatti, E. M. Clarke, O. Strichman, and Y. Zhu, “Bounded model checking,” ser. Advances in Computers.   Elsevier, 2003, pp. 117–148.
  85. S. Drzevitzky, “Proof-carrying hardware: Runtime formal verification for secure dynamic reconfiguration,” in 2010 International Conference on Field Programmable Logic and Applications, 2010, pp. 255–258.
  86. L. De Moura and N. Bjørner, “Z3: An Efficient SMT Solver,” in Proceedings of the Theory and Practice of Software, 14th International Conference on Tools and Algorithms for the Construction and Analysis of Systems.   Springer-Verlag, 2008, p. 337–340.
  87. INRIA, “The coq proof assistant,” last accessed: 11/20/2023. [Online]. Available: https://coq.inria.fr/
  88. Accellera, “Universal Verification Methodology (UVM),” last accessed 11/19/2023. [Online]. Available: https://www.accellera.org/
  89. C. Ioannides, G. Barrett, and K. Eder, “Introducing xcs to coverage directed test generation,” in 2011 IEEE International High Level Design Validation and Test Workshop, 2011, pp. 57–64.
  90. J. Yuan, C. Pixley, A. Aziz, and K. Albin, “A framework for constrained functional verification,” in ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486), 2003, pp. 142–145.
  91. Cocotb, “Use cocotb to test and verify chip designs in python. productive, and with a smile.” last accessed: 11/20/2023. [Online]. Available: https://www.cocotb.org/
  92. M. Teplitsky, A. Metodi, and R. Azaria, “Coverage driven distribution of constrained random stimuli,” 2015.
  93. O. Guzey and L.-C. Wang, “Coverage-directed test generation through automatic constraint extraction,” in 2007 IEEE International High Level Design Validation and Test Workshop, 2007, pp. 151–158.
  94. Verilator, “Welcome to verilator,” last accessed: 11/18/2023. [Online]. Available: https://www.veripool.org/verilator/
  95. J. Wang, B. Chen, L. Wei, and Y. Liu, “Skyfire: Data-driven seed generation for fuzzing,” in IEEE Symposium on Security and Privacy (SP), 2017.
  96. M. Böhme, V.-T. Pham, M.-D. Nguyen, and A. Roychoudhury, “Directed greybox fuzzing,” in ACM SIGSAC Conference on Computer and Communications Security, 2017.
  97. Google, “Honggfuzz,” last accessed: 11/18/2023. [Online]. Available: https://github.com/google/honggfuzz
  98. A. Geralis, “Libfuzzer,” last accessed: 11/18/2023. [Online]. Available: https://github.com/planetis-m/libfuzzer
  99. Chisel, “Chisel/FIRRTL hardware compiler framework,” last accessed: 11/20/2023. [Online]. Available: https://www.chisel-lang.org/
  100. OpenRISC, “mor1kx - an openrisc processor IP core,” last accessed: 11/18/2023. [Online]. Available: https://github.com/openrisc/mor1kx
  101. R.-V. W. Group, “Spike ISA simulator,” last accessed: 11/18/2023. [Online]. Available: https://github.com/riscv-software-src/riscv-isa-sim
  102. M. R. Clarkson and F. B. Schneider, “Hyperproperties,” in 2008 21st IEEE Computer Security Foundations Symposium, 2008, pp. 51–65.
  103. S. Canakci, L. Delshadtehrani, F. Eris, M. B. Taylor, M. Egele, and A. Joshi, “Directfuzz: Automated test generation for rtl designs using directed graybox fuzzing,” in 2021 58th ACM/IEEE Design Automation Conference (DAC), 2021, pp. 529–534.
  104. MITRE Corportation, “CVE-2023-3953 improper restriction of operations,” last accessed: 11/20/2023. [Online]. Available: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2023-3953
  105. C.Alliance, “Flexible internal representation for rtl,” last accessed: 11/20/2023. [Online]. Available: https://github.com/chipsalliance/firrtl
  106. GNU, “The GNU assembler,” last accessed: 11/18/2023. [Online]. Available: https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_node/as_3.html
  107. J. M. Vern Paxson, Will Estes, “Lexical analysis with flex, for flex 2.6.2,” last accessed: 11/20/2023. [Online]. Available: https://westes.github.io/flex/manual/
  108. MITRE Corportation, “Uncontrolled resource consumption,” last accessed: 11/20/2023. [Online]. Available: https://cwe.mitre.org/data/definitions/400.html
  109. Openhwgroup, last accessed 11/19/2023. [Online]. Available: https://github.com/openhwgroup/cva6
  110. H. Wong, V. Betz, and J. Rose, “Quantifying the gap between fpga and custom cmos to aid microarchitectural design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 10, pp. 2067–2080, 2014.
  111. MITRE Corportation, “Incorrect control flow scoping,” last accessed: 11/20/2023. [Online]. Available: https://cwe.mitre.org/data/definitions/705.html
  112. OSDev, “Cpu registers x86,” last accessed: 11/20/2023. [Online]. Available: https://wiki.osdev.org/CPU_Registers_x86#Control_Registers
  113. Five EmbedDev, “Control and status registers (csrs),” last accessed: 11/20/2023. [Online]. Available: https://five-embeddev.com/quickref/csrs.html
  114. MITRE Corportation, “CVE-2023-29856 in D-link,” last accessed: 11/20/2023. [Online]. Available: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2023-29856
  115. National Vulnerability Database - ARM, “CVE-2017-5927 in ARM processors,” last accessed: 11/20/2023. [Online]. Available: https://nvd.nist.gov/vuln/detail/CVE-2017-5927
  116. MITRE Corportation, “CVE-2023-32342 in IBM X-Force,” last accessed: 11/20/2023. [Online]. Available: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2023-32342
  117. NIST National Vulnerability Database - HP, “CVE-2004-2439 in HP printers,” last accessed: 11/18/2023. [Online]. Available: https://nvd.nist.gov/vuln/detail/CVE-2004-2439
  118. NVIDIA, “CVE-2021-1088 in NVIDIA GPU and Tegra hardware,” last accessed: 11/20/2023. [Online]. Available: https://nvidia.custhelp.com/app/answers/detail/a_id/5263
  119. MIPS Technologies, “MIPS,” last accessed: 11/20/2023. [Online]. Available: https://mips.com/
  120. Ken Vollmar, “Mars,” last accessed: 11/20/2023. [Online]. Available: https://courses.missouristate.edu/kenvollmar/mars/
  121. James Larus, “SPIM: A MIPS32 Simulator,” last accessed: 11/20/2023. [Online]. Available: https://spimsimulator.sourceforge.net/
  122. C. Trippel, Y. A. Manerkar, D. Lustig, M. Pellauer, and M. Martonosi, “Tricheck: Memory model verification at the trisection of software, hardware, and isa,” Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2016.
  123. C. Domas, “Breaking the x86 isa,” 2017.
  124. M. Bartley and Chakravarthi, “Shortage of verification resources in the semiconductor industry,” last accessed: 11/20/2023. [Online]. Available: https://www.design-reuse.com/articles/28108/shortage-of-verification-resources-in-the-semiconductor-industry.html
  125. Zippa, “Verification engineer projected growth in the united states,” last accessed: 11/18/2023.
  126. Google, “Hardware product sprint,” last accessed: 11/18/2023. [Online]. Available: https://buildyourfuture.withgoogle.com/programs/hps

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