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Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate (2403.04981v1)

Published 8 Mar 2024 in cs.ET

Abstract: In this work, we propose a dual-port cell design to address the pass disturb in vertical NAND storage, which can pass signals through a dedicated and string-compatible pass gate. We demonstrate that: i) the pass disturb-free feature originates from weakening of the depolarization field by the pass bias at the high-${V}{TH}$ (HVT) state and the screening of the applied field by channel at the low-${V}{TH}$ (LVT) state; ii) combined simulations and experimental demonstrations of dual-port design verify the disturb-free operation in a NAND string, overcoming a key challenge in single-port designs; iii) the proposed design can be incorporated in a highly scaled vertical NAND FeFET string and the pass gate can be incorporated into the existing 3D NAND with the negligible overhead of the pass gate interconnection through a global bottom pass gate contact in the substrate.

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Summary

  • The paper presents a dual-port FeFET design that decouples pass bias from memory operations to effectively minimize disturb issues in VNAND storage.
  • Experimental results from FEOL/BEOL FeFET tests and TCAD simulations validate the design's ability to maintain stable memory states under aggressive scaling.
  • The study paves the way for more reliable, high-density VNAND storage solutions with minimal overhead and enhanced performance.

Enhancing Vertical NAND Storage Through Dual-Port Cell Design

Introduction

The paper introduces a dual-port cell design as a solution to the pass disturb problem in vertical NAND (VNAND) storage, showcasing both theoretical and empirical support for its viability. This design, specifically tailored for ferroelectric field-effect transistor (FeFET) based storage, facilitates signal passing through a dedicated pass gate, thereby addressing the long-standing challenge associated with traditional single-port designs.

Rationale Behind Dual-Port FeFET

VNAND technology, despite its high density and cost-effectiveness, wrestles with the issue of escalating memory state disturbances during array operation under aggressive scaling. The new design diverges from conventional single-port configurations by integrating an independent pass gate with non-ferroelectric gate dielectric. This structural innovation is not only compatible with the current VNAND arrays but also introduces minimal overhead when embedding the additional gate. A core attribute of the design is its ability to mitigate pass disturb challenges inherently present in single-port configurations, ensuring high reliability for future VNAND applications.

Mechanisms of Disturb-Free Operation

The paper explores the operational mechanisms underlying the disturb-free features, attributing them to the decoupling of pass and program operations across two gates. Theoretical analyses supplemented by device simulations confirm the hypothesized benefits, observing substantial reductions in depolarization field effects during pass operations in the high-V_TH (HVT) state and efficient screening in the low-V_TH (LVT) state. This effectively eliminates adverse impact on memory states during the pass process, further validated through experimental results on both front-end-of-line (FEOL) and back-end-of-line (BEOL) FeFETs.

Experimental Verification and Results

The investigation extends beyond theoretical insights, demonstrating through FEOL and BEOL FeFETs that dual-port design can indeed achieve its purported disturb-free operation. The models tested encompass various forms and substrates, including integration on a 22 nm FDSOI platform and deployment of an amorphous metal oxide thin film channel for BEOL FeFETs. The results consistently exhibit negligible disturb to memory states when leveraging the dual-port design, especially compared to single-port counterparts where significant disturbances were observed.

Realizing Dual-Port VNAND Operation

A pivotal aspect of this paper is its exploration into the application of dual-port FeFET within a VNAND string through TCAD simulations. It outlines a feasible integration strategy that demonstrates both the operational efficacy and minimal overhead of transitioning to a dual-port system in the vertical NAND architecture. These simulations provide a compelling argument for the implementation of dual-port FeFETs in scaling VNAND technology, affirming the potential for disturb-free operations in densely packed memory arrays.

Implications and Future Directions

The proposed dual-port cell design promises a substantial leap toward solving one of the most critical challenges in scaling VNAND technology— the pass disturb issue. By effectively decoupling pass bias from the memory gate, this design paves the way for more reliable, densely packed VNAND storage solutions. The research points to great potential in further exploring and optimizing dual-port VNAND configurations, pushing the boundaries of data storage scalability and reliability.

Conclusion

This work proffers a novel dual-port FeFET design as a viable solution to the longstanding pass disturb problem in VNAND storage. Through comprehensive theoretical and experimental investigations, it establishes a strong foundation for the practical application of this design in future VNAND developments. The paper’s findings not only enrich the current understanding of FeFET-based storage systems but also offer a promising pathway to enhancing the performance and reliability of future vertical NAND memory technologies.

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