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Utilizing Layout Effects for Analog Logic Locking (2401.06508v1)

Published 12 Jan 2024 in cs.CR and cs.AR

Abstract: While numerous obfuscation techniques are available for securing digital assets in the digital domain, there has been a notable lack of focus on protecting Intellectual Property (IP) in the analog domain. This is primarily due to the relatively smaller footprint of analog components within an Integrated Circuit (IC), with the majority of the surface dedicated to digital elements. However, despite their smaller nature, analog components are highly valuable IP and warrant effective protection. In this paper, we present a groundbreaking method for safeguarding analog IP by harnessing layout-based effects that are typically considered undesirable in IC design. Specifically, we exploit the impact of Length of Oxide Diffusion and Well Proximity Effect on transistors to fine-tune critical parameters such as transconductance (gm) and threshold voltage (Vth). These parameters remain concealed behind key inputs, akin to the logic locking approach employed in digital ICs. Our research explores the application of layout-based effects in two commercial CMOS technologies, namely a 28nm and a 65nm node. To demonstrate the efficacy of our proposed technique, we implement it for locking an Operational Transconductance Amplifier. Extensive simulations are performed, evaluating the obfuscation strength by applying a large number of key sets (over 50,000 and 300,000). The results exhibit a significant degradation in performance metrics, such as open-loop gain (up to 130dB), phase margin (up to 50 degrees), 3dB bandwidth (approximately 2.5MHz), and power consumption (around 1mW) when incorrect keys are employed. Our findings highlight the advantages of our approach as well as the associated overhead.

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References (28)
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Technical report (April 2008) Colombier and Bossuet [2014] Colombier, B., Bossuet, L.: Survey of hardware protection of design data for integrated circuits and intellectual properties. IET Computers & Digital Techniques 8(6), 274–287 (2014) Rajendran et al. [2014] Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jacob, N., Merli, D., Heyszl, J., Sigl, G.: Hardware trojans: current challenges and approaches. IET Computers & Digital Techniques 8(6), 264–273 (2014) Keshavarz et al. [2018] Keshavarz, S., Yu, C., Ghandali, S., Xu, X., Holcomb, D.: Survey on applications of formal methods in reverse engineering and intellectual property protection. Journal of Hardware and Systems Security 2(3), 214–224 (2018) SEMI [2008] SEMI: White paper: Innovation at Risk — Intellectual Property Challenges and Opportunities. Technical report (April 2008) Colombier and Bossuet [2014] Colombier, B., Bossuet, L.: Survey of hardware protection of design data for integrated circuits and intellectual properties. IET Computers & Digital Techniques 8(6), 274–287 (2014) Rajendran et al. [2014] Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Keshavarz, S., Yu, C., Ghandali, S., Xu, X., Holcomb, D.: Survey on applications of formal methods in reverse engineering and intellectual property protection. Journal of Hardware and Systems Security 2(3), 214–224 (2018) SEMI [2008] SEMI: White paper: Innovation at Risk — Intellectual Property Challenges and Opportunities. Technical report (April 2008) Colombier and Bossuet [2014] Colombier, B., Bossuet, L.: Survey of hardware protection of design data for integrated circuits and intellectual properties. IET Computers & Digital Techniques 8(6), 274–287 (2014) Rajendran et al. [2014] Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE SEMI: White paper: Innovation at Risk — Intellectual Property Challenges and Opportunities. Technical report (April 2008) Colombier and Bossuet [2014] Colombier, B., Bossuet, L.: Survey of hardware protection of design data for integrated circuits and intellectual properties. IET Computers & Digital Techniques 8(6), 274–287 (2014) Rajendran et al. [2014] Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. 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In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. 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[2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. 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IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. 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[2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. 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[2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. 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Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). 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In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  2. Jacob, N., Merli, D., Heyszl, J., Sigl, G.: Hardware trojans: current challenges and approaches. IET Computers & Digital Techniques 8(6), 264–273 (2014) Keshavarz et al. [2018] Keshavarz, S., Yu, C., Ghandali, S., Xu, X., Holcomb, D.: Survey on applications of formal methods in reverse engineering and intellectual property protection. Journal of Hardware and Systems Security 2(3), 214–224 (2018) SEMI [2008] SEMI: White paper: Innovation at Risk — Intellectual Property Challenges and Opportunities. Technical report (April 2008) Colombier and Bossuet [2014] Colombier, B., Bossuet, L.: Survey of hardware protection of design data for integrated circuits and intellectual properties. IET Computers & Digital Techniques 8(6), 274–287 (2014) Rajendran et al. [2014] Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. 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In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Keshavarz, S., Yu, C., Ghandali, S., Xu, X., Holcomb, D.: Survey on applications of formal methods in reverse engineering and intellectual property protection. Journal of Hardware and Systems Security 2(3), 214–224 (2018) SEMI [2008] SEMI: White paper: Innovation at Risk — Intellectual Property Challenges and Opportunities. Technical report (April 2008) Colombier and Bossuet [2014] Colombier, B., Bossuet, L.: Survey of hardware protection of design data for integrated circuits and intellectual properties. IET Computers & Digital Techniques 8(6), 274–287 (2014) Rajendran et al. [2014] Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE SEMI: White paper: Innovation at Risk — Intellectual Property Challenges and Opportunities. Technical report (April 2008) Colombier and Bossuet [2014] Colombier, B., Bossuet, L.: Survey of hardware protection of design data for integrated circuits and intellectual properties. IET Computers & Digital Techniques 8(6), 274–287 (2014) Rajendran et al. [2014] Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Colombier, B., Bossuet, L.: Survey of hardware protection of design data for integrated circuits and intellectual properties. IET Computers & Digital Techniques 8(6), 274–287 (2014) Rajendran et al. [2014] Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). 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[2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. 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[2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). 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IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
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[2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. 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[2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE SEMI: White paper: Innovation at Risk — Intellectual Property Challenges and Opportunities. Technical report (April 2008) Colombier and Bossuet [2014] Colombier, B., Bossuet, L.: Survey of hardware protection of design data for integrated circuits and intellectual properties. IET Computers & Digital Techniques 8(6), 274–287 (2014) Rajendran et al. [2014] Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Colombier, B., Bossuet, L.: Survey of hardware protection of design data for integrated circuits and intellectual properties. IET Computers & Digital Techniques 8(6), 274–287 (2014) Rajendran et al. [2014] Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. 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In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. 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IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. 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IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
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[2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). 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[2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. 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[2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  5. Colombier, B., Bossuet, L.: Survey of hardware protection of design data for integrated circuits and intellectual properties. IET Computers & Digital Techniques 8(6), 274–287 (2014) Rajendran et al. [2014] Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. 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In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. 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[2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. 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[2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. 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[2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. 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[2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  6. Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE 102(8), 1266–1282 (2014) Roy et al. [2010] Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). 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[2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. 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[2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. 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[2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  7. Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010) Sanabria-Borbon et al. [2020] Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  8. Sanabria-Borbon, A., Jayasankaran, N.G., Lee, S., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Schmitt trigger-based key provisioning for locking analog/rf integrated circuits. In: 2020 IEEE International Test Conference (ITC), pp. 1–10 (2020). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. 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[2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  9. Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Hoe et al. [2014] Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Hoe, D.H., Rajendran, J., Karri, R.: Towards secure analog designs: A secure sense amplifier using memristors. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 516–521 (2014). IEEE Rao and Savidis [2017] Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). 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Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. 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[2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
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[2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. 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Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. 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Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. 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[2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  11. Rao, V.V., Savidis, I.: Protecting analog circuits with parameter biasing obfuscation. In: 2017 18th IEEE Latin American Test Symposium (LATS), pp. 1–6 (2017). IEEE Wang et al. [2017] Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Wang, J., Shi, C., Sanabria-Borbon, A., Sánchez-Sinencio, E., Hu, J.: Thwarting analog ic piracy via combinational locking. In: 2017 IEEE International Test Conference (ITC), pp. 1–10 (2017). IEEE Nimmalapudi et al. [2020] Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. 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IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. 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IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. 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[2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  13. Nimmalapudi, S.G.R., Volanis, G., Lu, Y., Antonopoulos, A., Marshall, A., Makris, Y.: Range-controlled floating-gate transistors: A unified solution for unlocking and calibrating analog ics. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 286–289 (2020). IEEE Ash-Saki and Ghosh [2018] Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). 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[2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Ash-Saki, A., Ghosh, S.: How multi-threshold designs can protect analog ips. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), pp. 464–471 (2018). IEEE Volanis et al. [2019] Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. 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[2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
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[2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. 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IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  15. Volanis, G., Lu, Y., Nimmalapudi, S.G.R., Antonopoulos, A., Marshall, A., Makris, Y.: Analog performance locking through neural network-based biasing. In: 2019 IEEE 37th VLSI Test Symposium (VTS), pp. 1–6 (2019). IEEE Elshamy et al. [2020] Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. 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[2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  16. Elshamy, M., Sayed, A., Louërat, M.-M., Rhouni, A., Aboushady, H., Stratigopoulos, H.-G.: Securing programmable analog ics against piracy. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 61–66 (2020). IEEE Tlili et al. [2022] Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. 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IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  17. Tlili, M., Sayed, A., Mahmoud, D., Louërat, M.-M., Aboushady, H., Stratigopoulos, H.-G.: Anti-piracy of analog and mixed-signal circuits in fd-soi. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 423–428 (2022). IEEE Jayasankaran et al. [2018] Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. 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[2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. 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Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  18. Jayasankaran, N.G., Borbon, A.S., Sanchez-Sinencio, E., Hu, J., Rajendran, J.: Towards provably-secure analog and mixed-signal locking against overproduction. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018) Leonhard et al. [2019] Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  19. Leonhard, J., Yasin, M., Turk, S., Nabeel, M.T., Louërat, M.-M., Chotin-Avot, R., Aboushady, H., Sinanoglu, O., Stratigopoulos, H.-G.: Mixlock: Securing mixed-signal circuits via logic locking. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 84–89 (2019). IEEE Rao et al. [2020] Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rao, V.V., Juretus, K., Savidis, I.: Security vulnerabilities of obfuscated analog circuits. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2020). IEEE Jayasankaran et al. [2020] Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. 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IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
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IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. 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  21. Jayasankaran, N.G., Sanabria-Borbón, A., Abuellil, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J.: Breaking analog locking techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(10), 2157–2170 (2020) Leonhard et al. [2021] Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  22. Leonhard, J., Elshamy, M., Louërat, M.-M., Stratigopoulos, H.-G.: Breaking analog biasing locking techniques via re-synthesis. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, pp. 555–560 (2021) Acharya et al. [2020] Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  23. Acharya, R.Y., Chowdhury, S., Ganji, F., Forte, D.: Attack of the genes: Finding keys and parameters of locked analog ics using genetic algorithm. In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 284–294 (2020). IEEE Aljafar et al. [2022] Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  24. Aljafar, M.J., Azaïs, F., Flottes, M.-L., Pagliarini, S.: Leveraging layout-based effects for locking analog ics. In: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. ASHES’22, pp. 5–13. Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3560834.3563826 Intelligence Advanced Research Projects Activity (IARPA) [2016] Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  25. Intelligence Advanced Research Projects Activity (IARPA): Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). https://www.iarpa.gov/index.php/research-programs/raven Rajendran et al. [2012] Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  26. Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: A fault analysis perspective. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 953–958 (2012). IEEE Yasin et al. [2017] Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  27. Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8(2), 517–532 (2017) Subramanyan et al. [2015] Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE
  28. Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015). IEEE

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