REVERSIM: An Open-Source Environment for the Controlled Study of Human Aspects in Hardware Reverse Engineering (2309.05740v3)
Abstract: Hardware Reverse Engineering (HRE) is a technique for analyzing integrated circuits. Experts employ HRE for security-critical tasks, like detecting Trojans or intellectual property violations, relying not only on their experience and customized tools but also on their cognitive abilities. In this work, we introduce ReverSim, a software environment that models key HRE subprocesses and integrates standardized cognitive tests. ReverSim enables quantitative studies with easier-to-recruit non-experts to uncover cognitive factors relevant to HRE. We empirically evaluated ReverSim in three studies. Semi-structured interviews with 14 HRE professionals confirmed its comparability to real-world HRE processes. Two online user studies with 170 novices and intermediates revealed effective differentiation of participant performance across a spectrum of difficulties, and correlations between participants' cognitive processing speed and task performance. ReverSim is available as open-source software, providing a robust platform for controlled experiments to assess cognitive processes in HRE, potentially opening new avenues for hardware protection.
- DANA universal dataflow analysis for gate-level netlist reverse engineering. IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2020(4):309–336, 2020.
- A survey of algorithmic methods in IC reverse engineering. Journal of Cryptographic Engineering, 11(3):299–315, 2021.
- Hardware obfuscation: Techniques and open challenges. In Foundations of Hardware IP Protection, pages 105–123. Springer, 2017.
- An exploratory study of hardware reverse engineering — technical and cognitive processes. In Sixteenth Symposium on Usable Privacy and Security, SOUPS 2020, August 7-11, 2020, pages 285–300. USENIX Association, 2020.
- Administration and interpretation of the trail making test. Nature Protocols, 1(5):2277–2281, December 2006.
- Understanding integrated circuits. IEEE Design & Test of Computers, 16(2):26–37, 1999.
- Secure logic locking and configuration with camouflaged programmable micro netlists, June 23 2020. US Patent 10,691,860.
- Circuit camouflage integration for hardware IP protection. In The 51st Annual Design Automation Conference 2014, DAC ’14, San Francisco, CA, USA, June 1-5, 2014, pages 153:1–153:5. ACM, 2014.
- Lee J Cronbach. Coefficient alpha and the internal structure of tests. psychometrika, 16(3):297–334, 1951.
- European Comission. A Chips Act for Europe – Comission Staff Working Document, may 2022.
- Hardware reverse engineering: Overview and open challenges. In IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, pages 88–94. IEEE, 2017.
- On the difficulty of FSM-based hardware obfuscation. IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2018(3):293–330, 2018.
- HAL – the missing piece of the puzzle for hardware reverse engineering, trojan detection and insertion. IEEE Transactions on Dependable and Secure Computing, 16(3):498–510, 2019.
- Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering. IEEE Design & Test of Computers, 16(3):72–80, 1999.
- From silicon to simulation: A full decomposition of a fabricated 130 nm serial peripheral interface for establishing an assurance baseline root-of-trust. In 2020 IEEE Physical Assurance and Inspection of Electronics (PAINE). IEEE, December 2020.
- Thomas Kuenemund. Semiconductor chip using logic circuitry including complementary fets for reverse engineering protection, July 9 2019. US Patent 10,347,630.
- A theory of reverse engineering and its application to boolean systems. Journal of Cognitive Psychology, 25(4):365–389, 2013.
- Philipp Mayring. Qualitative content analysis: Demarcation, varieties, developments. Forum: Qualitative Social Research, 20(3):1–26, 2019.
- Equivalence of computerized and paper-and-pencil cognitive ability tests: A meta-analysis. Psychological Bulletin, 114(3):449–458, November 1993.
- Netlist reverse engineering for high-level functionality reconstruction. In 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, January 25-28, 2016, pages 655–660. IEEE, 2016.
- Wolf Dieter Oswald. Zahlen-Verbindungs-Test ZVT. 3., überarbeitete und neu normierte Auflage. Hogrefe, 2016.
- Red team vs. blue team: A real-world hardware trojan detection case study across four modern cmos technology generations. In 2023 IEEE Symposium on Security and Privacy (SP), pages 56–74, Los Alamitos, CA, USA, may 2023. IEEE Computer Society.
- A survey on chip to system reverse engineering. ACM Journal on Emerging Technologies in Computing Systems, 13(1):6:1–6:34, 2016.
- Large-area automated layout extraction methodology for full-IC reverse engineering. Journal of Hardware and Systems Security, 2(4):322–332, 2018.
- Power reduction via separate synthesis and physical libraries. In Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011, pages 627–632. ACM, 2011.
- M. G. Rekoff. On reverse engineering. IEEE Transactions on Systems, Man, and Cybernetics, 15(2):244–252, 1985.
- Nonlinearity bounds and constructions of resilient boolean functions. In Advances in Cryptology - CRYPTO 2000, 20th Annual International Cryptology Conference, Santa Barbara, California, USA, August 20-24, 2000, Proceedings, pages 515–532. Springer, 2000.
- Senate of the United States. CHIPS and Science Act 2022 (P.L. 117-167), july 2022.
- Covert gates: Protecting integrated circuits with undetectable camouflaging. IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2019(3):86–118, 2019.
- Extracting functional modules from flattened gate-level netlist. In International Symposium on Communications and Information Technologies, ISCIT 2012, Gold Coast, Australia, October 2-5, 2012, pages 538–543. IEEE, 2012.
- A highly efficient method for extracting FSMs from flattened gate-level netlist. In International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pages 2610–2613. IEEE, 2010.
- Reverse engineering digital circuits using structural and functional analyses. IEEE Transactions on Emerging Topics in Computing, 2(1):63–80, 2014.
- Making sense of cronbach’s alpha. International journal of medical education, 2:53, 2011.
- On the impact of automating the ic analysis process. Technical report, Texplained SARL, 2015.
- The state-of-the-art in IC reverse engineering. In Cryptographic Hardware and Embedded Systems - CHES 2009, 11th International Workshop, Lausanne, Switzerland, September 6-9, 2009, Proceedings, pages 363–381. Springer, 2009.
- Philip A. Vernon. Der zahlen-verbindungs-test and other trail-making correlates of general intelligence. Personality and Individual Differences, 14(1):35–40, January 1993.
- Highway to HAL: Open-sourcing the first extendable gate-level netlist reverse engineering framework. In Proceedings of the 16th ACM International Conference on Computing Frontiers, CF 2019, Alghero, Italy, April 30 - May 2, 2019, pages 392–397. ACM, 2019.
- A look at the dark side of hardware reverse engineering — a case study. In IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, pages 95–100. IEEE, 2017.
- Method and apparatus for camouflaging an integrated circuit using virtual camouflage cells, October 27 2020. US Patent 10,817,638.
- B. L. Welch. On the comparison of several mean values: An alternative approach. Biometrika, 38(3/4):330, December 1951.
- Towards cognitive obfuscation: Impeding hardware reverse engineering based on psychological insights. In Proceedings of the 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, January 21-24, 2019, pages 104–111. ACM, 2019.
- Promoting the acquisition of hardware reverse engineering skills. In IEEE Frontiers in Education Conference, FIE 2019, Cincinnati, OH, USA, October 16-19, 2019, pages 1–9. IEEE, 2019.
- Teaching hardware reverse engineering: Educational guidelines and practical insights. In IEEE International Conference on Teaching, Assessment, and Learning for Engineering, TALE 2018, Wollongong, Australia, December 4-7, 2018, pages 438–445. IEEE, 2018.
- The anatomy of hardware reverse engineering: An exploration of human factors during problem solving. ACM Trans. Comput.-Hum. Interact., 30(4), sep 2023.