Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information (2303.07405v1)

Abstract: Reverse engineering of FPGA based designs from the flattened LUT level netlist to high level RTL helps in verification of the design or in understanding legacy designs. We focus on flattened netlists for FPGA devices from Xilinx 7 series and Zynq 7000. We propose a design element grouping algorithm that makes use of the location information of the elements on the physical device after place and route. The proposed grouping algorithm gives clusters with average NMI of 0.73 for groupings including all element types. The benchmarks chosen include a range of designs from communication, arithmetic units, processors and DSP processing units.