HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips (2209.10198v1)

Abstract: DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh operations degrade system performance by interfering with memory accesses. As DRAM chip density increases with technology node scaling, refresh operations also increase because: 1) the number of DRAM rows in a chip increases; and 2) DRAM cells need additional refresh operations to mitigate bit failures caused by RowHammer, a failure mechanism that becomes worse with technology node scaling. Thus, it is critical to enable refresh operations at low performance overhead. To this end, we propose a new operation, Hidden Row Activation (HiRA), and the HiRA Memory Controller (HiRA-MC). HiRA hides a refresh operation's latency by refreshing a row concurrently with accessing or refreshing another row within the same bank. Unlike prior works, HiRA achieves this parallelism without any modifications to off-the-shelf DRAM chips. To do so, it leverages the new observation that two rows in the same bank can be activated without data loss if the rows are connected to different charge restoration circuitry. We experimentally demonstrate on 56% real off-the-shelf DRAM chips that HiRA can reliably parallelize a DRAM row's refresh operation with refresh or activation of any of the 32% of the rows within the same bank. By doing so, HiRA reduces the overall latency of two refresh operations by 51.4%. HiRA-MC modifies the memory request scheduler to perform HiRA when a refresh operation can be performed concurrently with a memory access or another refresh. Our system-level evaluations show that HiRA-MC increases system performance by 12.6% and 3.73x as it reduces the performance degradation due to periodic refreshes and refreshes for RowHammer protection (preventive refreshes), respectively, for future DRAM chips with increased density and RowHammer vulnerability.

• The paper introduces HiRA, a method that concurrently activates two DRAM rows to parallelize refresh operations using existing DRAM commands.
• It achieves a 51.4% reduction in refresh latency and boosts performance by up to 12.6% in high-density DRAM systems.
• The study also proposes the HiRA-MC controller, which schedules memory and refresh requests to ensure reliable operation on commercial SK Hynix chips.

HiRA: Hidden Row Activation for Reducing Refresh Latency in DRAM Chips

This paper addresses the escalating challenge of refresh operations in DRAM technology, focusing on the increasing performance overhead in high-density DRAM chips due to regular refresh cycles and the mitigation of RowHammer vulnerabilities. As DRAM cell densities increase, so do the demands for refresh operations, leading to considerable performance degradations. Standard approaches to tackle these challenges often require hardware modifications, making them unsuitable for existing DRAM systems. This paper introduces a novel approach called HiRA (Hidden Row Activation) that enables the concurrent activation of two DRAM rows, effectively overlapping refresh operations with accesses or further refreshes, without necessitating changes to DRAM chip design.

Key Contributions

1. Innovative Parallelization Technique: HiRA uses existing DRAM commands in a carefully timed sequence to achieve refresh and access parallelization in the same bank. The ability to concurrently perform these operations without additional hardware modification is seminal, demonstrating the possibility for immediate application in current DRAM systems.
2. Significant Latency Reduction: By demonstrating the feasibility of overlapping a refresh operation with another within a DRAM bank, HiRA reduces the latency for two consecutive DRAM refresh operations by approximately 51.4%. Such an improvement showcases the potential for combining HiRA with existing DRAM infrastructures to notably boost memory performance.
3. HiRA-MC Controller Design: The paper proposes HiRA-MC, a memory controller that intelligently schedules memory and refresh requests to exploit HiRA's capabilities. HiRA-MC ensures timely execution of both periodic and preventative DRAM refresh operations, enhancing system performance without compromising refresh deadlines or RowHammer protection.
4. Experimental Validation: The authors provide a comprehensive experimental evaluation of HiRA on real DRAM chips from SK Hynix, discovering that the operation works reliably without erroneous data interference. This empirical evidence supports HiRA's practical applicability in DRAM designs without necessitating new fabrication processes or significant alterations to existing infrastructure.

Performance Implications

HiRA and its implementation, HiRA-MC, significantly improve system performance, especially for DRAM systems with high row densities. Compared to traditional refresh techniques, HiRA offers up to a 12.6% performance increase when addressing periodic refresh overheads in scenarios with high DRAM capacity. Furthermore, for systems suffering from severe RowHammer vulnerabilities, HiRA provides a game-changing reduction in preventative refresh penalties, amplifying performance by up to 3.73 times in highly vulnerable conditions.

Limitations and Future Research

The paper notes the limitation that HiRA has been predominantly verified with DRAM chips from SK Hynix, suggesting vendor-specific capabilities might influence the generalizability of the approach. Future work could explore collaborations with other DRAM manufacturers to develop universally applicable techniques and further optimize DRAM operations. Additionally, the potential integration of HiRA with advanced DRAM architectures and the development of standardized support for such techniques can enhance DRAM scaling efforts in future memory technologies.

Conclusion

HiRA presents a highly effective and practical solution to some of the pressing concerns in DRAM refresh operations, offering tangible benefits for both system performance and security by addressing RowHammer vulnerabilities. This research suggests a path forward for leveraging existing DRAM architectures more efficiently, providing a promising direction for both academic research and industry application in the field of memory systems.