- The paper critiques the optimality of ternary logic by demonstrating that transistor counts in ternary circuits often surpass theoretical efficiency thresholds.
- The paper employs MOSFET-like CNTFET technology to rigorously compare the complexity of basic, arithmetic, and sequential circuits between ternary and binary systems.
- The paper finds that increased design complexity and power supply challenges in ternary circuits reinforce the practical superiority of binary logic in mainstream applications.
Analysis of Ternary Circuits vs. Binary Circuits for Computational Efficiency
The paper Ternary circuits: why R = 3 is not the Optimal Radix for Computation presents a detailed critique of the long-standing hypothesis that a radix of 3 (ternary logic) is optimal for computation, based on the proximity of 3 to the mathematical constant e (approximately 2.718). The paper, authored by Daniel Etiemble, employs MOSFET-like CNTFET technology to examine the efficiency of various ternary circuits compared to their binary counterparts, including inverters, arithmetic circuits, and memory cells.
Disproof of the Optimal Radix Hypothesis
The paper provides a rigorous quantitative assessment against the prevailing notion that ternary logic offers superior efficiency. The well-cited basis of this hypothesis is the work from 1984, which suggested that a radix equal to e minimizes hardware complexity. However, the paper argues that this conclusion is based on an overly simplistic model of system complexity that does not adequately reflect the real-world intricacies of electronic circuit design.
Comparative Analysis: Ternary vs. Binary
Transistor Count and Circuit Complexity
The paper conducts a comprehensive comparative analysis focused on the transistor count, which serves as a proxy for evaluating circuit complexity, chip area, and power dissipation. Ternary circuits are supposed to have an advantage in terms of interconnection complexity, given their ability to encode more states per signal. Theoretically, a ternary system should leverage an information ratio of log(3)/log(2) ≈ 1.58 compared to binary systems. However, the paper finds that ternary systems do not meet the necessary complexity thresholds that would capitalize on this advantage:
- Basic Logic Gates: The ternary implementations of inverters and logic gates generally exceed the transistor count ratio of 1.58, except in specific circumstances involving a ternary inverter design reliant on additional power supplies and continuous current paths—both problematic and typically inefficient in practice.
- Arithmetic Circuits: Ternary adders and multipliers show significantly higher transistor counts than their binary equivalents, with ternary adders and multipliers demonstrating ratios far exceeding the 1.58 mark essential for efficiency parity.
- Sequential Circuits and Memory Cells: Here too, any marginal benefits of ternary circuits, such as reduced wiring from fewer inputs/outputs, are offset by increased internal complexity and inefficiency.
Implications for Future Circuit Design
The paper concludes that while the theoretical appeal of ternary circuits is robust, practical considerations favor binary logic, primarily due to its superior efficiency in terms of hardware complexity and manufacturability. The limitations of ternary circuits are evident in the need for more transistors and challenges related to multiple voltage thresholds and increased power supply necessities. Consequently, binary circuits maintain their supremacy in mainstream digital electronics, driven by continuous advancements in CMOS technology and fabrication.
Future Prospects
Looking ahead, the paper implies that ternary and other multi-valued logic systems may only find niche applications where their specific advantages in solving certain classes of computational problems, like content-addressable memories, outweigh their complexity disadvantages. As computational requirements and technology innovate, the paper suggests that designs incorporating binary logic will continue to evolve, potentially integrating aspects of multi-valued logic only where meaningful advantages are clear.
The paper’s findings serve as a compelling reminder of the nuanced practical considerations in circuit design, signaling that theoretical assumptions must be rigorously tested against real-world engineering constraints. Researchers and practitioners in the field should continue to scrutinize the trade-offs between theoretical efficiency and practical viability in advancing both digital and analog logic design.