Inter-Tier Process Variation-Aware Monolithic 3D NoC Architectures

Abstract: Monolithic 3D (M3D) technology enables high density integration, performance, and energy-efficiency by sequentially stacking tiers on top of each other. M3D-based network-on-chip (NoC) architectures can exploit these benefits by adopting tier partitioning for intra-router stages. However, conventional fabrication methods are infeasible for M3D-enabled designs due to temperature related issues. This has necessitated lower temperature and temperature-resilient techniques for M3D fabrication, leading to inferior performance of transistors in the top tier and interconnects in the bottom tier. The resulting inter-tier process variation leads to performance degradation of M3D-enabled NoCs. In this work, we demonstrate that without considering inter-tier process variation, an M3D-enabled NoC architecture overestimates the energy-delay-product (EDP) on average by 50.8% for a set of SPLASH-2 and PARSEC benchmarks. As a countermeasure, we adopt a process variation aware design approach. The proposed design and optimization method distribute the intra-router stages and inter-router links among the tiers to mitigate the adverse effects of process variation. Experimental results show that the NoC architecture under consideration improves the EDP by 27.4% on average across all benchmarks compared to the process-oblivious design.

• The paper presents a process-aware design that strategically allocates intra-router stages and inter-router links to counteract inter-tier process variations in M3D NoCs.
• The paper utilizes the machine learning-based STAGE framework to optimize router configurations, resulting in a 27.4% improvement in the energy-delay product.
• The paper highlights that addressing inter-tier variations prevents overestimations of EDP by 50.8%, ensuring more reliable performance evaluation in high-density systems.

Inter-Tier Process Variation-Aware Monolithic 3D NoC Architectures

Introduction

The paper addresses the challenges and solutions associated with implementing Monolithic 3D (M3D) technology in network-on-chip (NoC) architectures. M3D technology enhances integration density and performance by stacking silicon layers vertically, leading to significant energy efficiency improvements over traditional planar designs. However, M3D fabrication faces hurdles such as temperature-related issues which adversely affect the electrical properties of transistors and interconnections across different tiers. This paper focuses on how inter-tier process variations impact the energy-delay product (EDP) of M3D NoCs and presents a process-aware design methodology to mitigate these effects.

Inter-Tier Process Variation Challenges

The M3D fabrication process involves low-temperature processing to prevent degradation of devices in the lower-tier, leading to inferior performance of upper-tier transistors and bottom-tier interconnects. The paper demonstrates how neglecting these variations can lead to significant overestimations—by about 50.8%—in EDP predictions based on standard SPLASH-2 and PARSEC benchmarks. Degraded performance is primarily due to higher resistivity interconnects in the bottom tier and reduced transistor efficiency in the top tier. These inter-tier discrepancies establish the necessity for a process variation-aware design approach for M3D NoCs to correctly estimate and optimize performance.

Design and Optimization Methodology

The paper proposes a method that distributes intra-router stages and inter-router links across various tiers to mitigate adverse effects of process variations. The study adopts a multi-tier architecture where each router's stages can be strategically allocated to either the top or bottom tier depending on the process variation implications. This adaptive placement reduces the detrimental impacts of transistor degradation in the top tier and interconnect resistance in the bottom tier.

To enhance the NoC's performance considering inter-tier variations, the authors utilize STAGE—an optimization framework based on machine learning. STAGE employs effective search techniques to identify optimal configurations and placements of routing resources across tiers, balancing the trade-offs between tier-specific performance issues.

Experimental Results

Experimental evaluations show that process-aware designs achieve a remarkable 27.4% average EDP improvement over process-oblivious designs. By applying this variation-aware design strategy, the architecture effectively compensates for tier-specific performance deficits and capitalizes on M3D integration's inherent advantages, such as reduced interconnect length and improved scaling.

Performance Trade-Offs and Practical Considerations

The paper highlights multiple performance trade-offs that accompany tier partitioning. For instance, while top-tier transistors offer lower delay with multitier stages, their degradation necessitates strategic balancing with bottom-tier routing resources.

From a practical implementation perspective, the research emphasizes using realistic manufacturing settings and benchmark traffic patterns to guide architectural partition decisions. This approach ensures substrate-specific challenges such as reduced carrier mobility and skin effect in vias are addressed through design innovations.

Conclusion

The paper advances understanding on designing NoC architectures that are resilient to process-induced variations inherent in current M3D technologies. By embracing a process-aware design philosophy, the research charts a path that significantly augments energy efficiency and performance reliability in high-density computing systems. Even under harsh process conditions, the proposed methodologies provide a viable path forward for deploying M3D technologies in scalable, high-performance NoCs. Future research may further explore optimizing for more complex multi-tier NoCs and extending these methodologies to broader application suites beyond SPLASH-2 and PARSEC benchmarks.