Implementation of Multilayer Perceptron Network with Highly Uniform Passive Memristive Crossbar Circuits (1712.01253v1)

Abstract: The progress in the field of neural computation hinges on the use of hardware more efficient than the conventional microprocessors. Recent works have shown that mixed-signal integrated memristive circuits, especially their passive ('0T1R') variety, may increase the neuromorphic network performance dramatically, leaving far behind their digital counterparts. The major obstacle, however, is relatively immature memristor technology so that only limited functionality has been demonstrated to date. Here we experimentally demonstrate operation of one-hidden layer perceptron classifier entirely in the mixed-signal integrated hardware, comprised of two passive 20x20 metal-oxide memristive crossbar arrays, board-integrated with discrete CMOS components. The demonstrated multilayer perceptron network, whose complexity is almost 10x higher as compared to previously reported functional neuromorphic classifiers based on passive memristive circuits, achieves classification fidelity within 3 percent of that obtained in simulations, when using ex-situ training approach. The successful demonstration was facilitated by improvements in fabrication technology of memristors, specifically by lowering variations in their I-V characteristics.

• The paper introduces a multilayer perceptron classifier using dual 20×20 passive memristive crossbar arrays integrated with discrete CMOS circuits.
• It achieves near-simulation-level classification fidelity with a 3% error margin while processing around 300,000 patterns per second.
• The work underscores energy efficiency improvements and scalable neuromorphic hardware potential through advanced memristor fabrication and 3D integration prospects.

Implementation of Multilayer Perceptron Network with Passive Memristive Crossbar Circuits

The paper by Merrikh Bayat et al. presents an advanced experimental demonstration of a single-hidden-layer perceptron classifier implemented entirely with mixed-signal integrated hardware comprising passive memristive crossbar circuits. Given the inherent inefficiencies of digital representations within neuromorphic systems when compared to their biological counterparts, this paper explores the use of metal-oxide memristors in enhancing neuromorphic network performance capabilities.

Key Contributions and Methodology

The key contribution of this work lies in the integration of two passive 20×20 memristive crossbar arrays with discrete CMOS components to form a multilayer perceptron (MLP). The implementation is notable for achieving near-simulation-level classification fidelity, within 3%, through an ex-situ training approach. This is facilitated by improvements in memristor fabrication technology that have reduced variability in I-V characteristics, thus allowing precise conductance tuning across the array.

The architecture employs approximately 10-fold more devices than previously reported efforts, underscoring advancements in complexity management for such systems. The memristors facilitate synaptic weights within the perceptron, while operational amplifier-based CMOS circuits handle neuron computations. The differential precision in achieving set and reset voltages within narrow distribution ranges further highlights advancements in memristive device uniformity.

Implications and Future Outlook

Practically, this research paves the way for highly energy-efficient neuromorphic hardware by integrating synaptic weights locally using passive memristive technology. The tangible reduction in energy and latency overheads for off-chip communications implies significant potential for large-scale artificial neural networks.

Theoretically, the implications of scaling neural network complexity through three-dimensional integration of passive memristors with CMOS circuits are profound. Such systems could achieve synaptic densities nearing biological levels, albeit with continued advancements in optimizing both crossbar dimensions and electrical resistance parameters. The potential for improving system-level energy efficiency and computational speed by multiple orders of magnitude becomes feasible with three-dimensional 10-nm memristor circuits.

Experimental Findings and Limitations

Experimentally, the paper reports a classification rate of approximately 300,000 patterns per second, a metric constrained mainly by analog signal propagation delays on the circuit board. The research also highlights the ongoing challenge of optimizing in-situ training protocols, noting the superiority of ex-situ approaches with hardware-aware training for pattern classification fidelity.

Looking forward, the paper projects that further scaling and integration of memristive technology could substantively bridge the efficiency gap between digital neuromorphic networks and their biological inspirations. Emulations of scalable inference processes with analog circuits present a significant frontier for future developments in AI hardware systems.

In summary, this paper establishes a critical milestone in the shift towards mixed-signal neuromorphic hardware, marking a significant step forward for analog computing in the field of AI. The demonstration's success with board-level integration sets a foundation upon which future advancements in energy-efficient, high-performance neuromorphic systems can be built.