Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms (1705.10292v1)

Abstract: The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy consumption. We would like to reduce the DRAM supply voltage more aggressively, to further reduce energy. Aggressive supply voltage reduction requires a thorough understanding of the effect voltage scaling has on DRAM access latency and DRAM reliability. In this paper, we take a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the supply voltage is lowered below the nominal voltage level specified by DRAM standards. Using an FPGA-based testing platform, we perform an experimental study of 124 real DDR3L (low-voltage) DRAM chips manufactured recently by three major DRAM vendors. We find that reducing the supply voltage below a certain point introduces bit errors in the data, and we comprehensively characterize the behavior of these errors. We discover that these errors can be avoided by increasing the latency of three major DRAM operations (activation, restoration, and precharge). We perform detailed DRAM circuit simulations to validate and explain our experimental findings. We also characterize the various relationships between reduced supply voltage and error locations, stored data patterns, DRAM temperature, and data retention. Based on our observations, we propose a new DRAM energy reduction mechanism, called Voltron. The key idea of Voltron is to use a performance model to determine by how much we can reduce the supply voltage without introducing errors and without exceeding a user-specified threshold for performance loss. Voltron reduces the average system energy by 7.3% while limiting the average system performance loss to only 1.8%, for a variety of workloads.

• The paper characterizes reduced-voltage operation in modern DRAM, showing errors emerge below a threshold but can be mitigated by increasing operation latencies.
• Building on their findings, the authors propose Voltron, which uses Array Voltage Scaling for energy savings and Performance-Aware Voltage Control to dynamically manage performance tradeoffs.
• Voltron achieves significant DRAM and system energy reductions with minimal performance loss, showing practical applicability and potential for other DRAM types such as LPDDR.

Characterization and Energy Reduction Mechanisms in Reduced-Voltage DRAM Operation

The paper Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms provides a comprehensive paper on the impact of supply voltage reduction in DDR3L DRAM chips and proposes an innovative approach to reduce energy consumption through voltage scaling only in the DRAM array. This research is critical in the context of reducing energy consumed by DRAM, which is a significant component of total power consumption in modern computing systems. Below, we discuss the insights gained from their experiments, the implications for DRAM technology, and the proposed mechanism to optimize DRAM energy efficiency without degrading system performance significantly.

Insights from Experimental Characterization

The authors identified key relationships between the supply voltage, reliability, and latency of DRAM operations:

1. Reliability at Low Voltage: They found that reducing supply voltage below a certain threshold, referred to as $V_{\text{min}}$, introduces bit errors. This threshold varies by vendor and device, and is influenced by fabrication processes and architectural designs.
2. Latency Adjustments: Errors induced by reduced voltage can be mitigated by increasing the latency of activation, restoration, and precharge operations. Circuit-level simulations (SPICE model) supported this by demonstrating how reduced voltage impacts the time required for these operations.
3. Error Locality: Errors tend to cluster spatially, occurring more frequently in specific regions of DRAM, allowing for potential targeted latency adjustments to maintain reliability.
4. Temperature and Data Retention: Elevated temperature marginally affects the necessary increase in latency, a factor that is vendor-dependent. Moreover, data retention time does not necessitate adjustment under lower voltage, given experiments up to 70°C comply with standard refresh intervals.

Voltron: Array Voltage Scaling and Performance Control

Based on their observations, the authors introduce Voltron, a novel mechanism comprising two primary components:

• Array Voltage Scaling (AVS): This reduces the DRAM array's supply voltage while keeping peripheral circuitry voltage constant, preserving memory channel frequency. The reduction in $V_{\text{array}}$ optimizes dynamic and static power components, mitigating potential performance loss by strategically increasing command latencies.
• Performance-Aware Voltage Control (PAVC): Employing a linear performance model, this mechanism ensures that array voltage reduction aligns with a user-defined threshold for acceptable performance degradation. By predicting application performance loss relative to memory demands (using MPKI and stall time metrics), PAVC dynamically selects voltage levels at runtime to balance energy savings and performance targets.

Practical Implications and Future Directions

This research offers several practical implications for DRAM design and operation:

• Energy Efficiency: Voltron achieves significant DRAM and system energy reductions with minimal performance penalties. Its applicability spans various workloads, making it a robust candidate for real-world DRAM energy optimization.
• Design Adaptability: The spatial error locality insight could lead to DRAM architectures that allow fine-grained control over latency settings, potentially enhancing systems' adaptability to varying operational conditions.
• Extended Applications: While focused on DDR3L, the approach has potential applicability in other DRAM technologies, such as LPDDR, which already operate within low-voltage domains. The insights from error clustering and latency-impact assurances provide pathways to advanced low-power DRAM designs.

Conclusion

This paper's experimental characterization offers novel insights into DRAM behavior under reduced-voltage operation, challenging traditional assumptions about latency and voltage reliability. Voltron exemplifies how understanding these relationships can lead to optimized mechanisms for energy efficiency. Future exploration could broaden these findings' application across DRAM variants and further refine performance-achieving methods by exploiting locality and dynamic control strategies. The paper's contributions represent significant progress in the pursuit of energy-efficient memory design solutions for next-generation computing systems.