Demonstration of a scaling advantage for a quantum annealer over simulated annealing (1705.07452v3)

Abstract: The observation of an unequivocal quantum speedup remains an elusive objective for quantum computing. The D-Wave quantum annealing processors have been at the forefront of experimental attempts to address this goal, given their relatively large numbers of qubits and programmability. A complete determination of the optimal time-to-solution (TTS) using these processors has not been possible to date, preventing definitive conclusions about the presence of a scaling advantage. The main technical obstacle has been the inability to verify an optimal annealing time within the available range. Here we overcome this obstacle and present a class of problem instances for which we observe an optimal annealing time using a D-Wave 2000Q processor over a range spanning up to more than $2000$ qubits. This allows us to perform an optimal TTS benchmarking analysis and perform a comparison to several classical algorithms, including simulated annealing, spin-vector Monte Carlo, and discrete-time simulated quantum annealing. We establish the first example of a scaling advantage for an experimental quantum annealer over classical simulated annealing: we find that the D-Wave device exhibits certifiably better scaling than simulated annealing, with $95\%$ confidence, over the range of problem sizes that we can test. However, we do not find evidence for a quantum speedup: simulated quantum annealing exhibits the best scaling by a significant margin. Our construction of instance classes with verifiably optimal annealing times opens up the possibility of generating many new such classes, paving the way for further definitive assessments of scaling advantages using current and future quantum annealing devices.

• The paper demonstrates a scaling advantage for a D-Wave quantum annealer over classical simulated annealing using specially designed problem instances that facilitate optimal annealing time discovery.
• While the D-Wave showed a scaling advantage over simulated annealing, it did not outperform discrete-time simulated quantum annealing, which scaled better.
• The study highlights the importance of problem instance design for assessing quantum hardware and suggests high temperature limits the annealer's performance.

Scaling Advantage of Quantum Annealer Compared to Classical Simulated Annealing

The paper "Demonstration of a scaling advantage for a quantum annealer over simulated annealing" investigates the performance of quantum annealers, specifically the D-Wave processors, in solving combinatorial optimization problems compared to classical algorithms like simulated annealing (SA). The goal is to establish a scaling advantage rather than achieving a full quantum speedup.

Overview and Objectives

One of the central aims of the paper is to overcome a significant technical obstacle that limits the ability to determine the optimal time-to-solution (TTS) using quantum annealers. The researchers accomplish this by creating a new class of problem instances that display an optimal annealing time within the accessible range of D-Wave's processors. This work provides the first example of a scaling advantage, as opposed to a definitive quantum speedup, for an experimental quantum annealer, achieved by contrasting its performance against classical simulated annealing.

Key Findings

1. Instance Construction: The paper introduces problem instances that combine spin-frustrated loops with a specially designed few-qubit "gadget." These elements promote tunneling energy barriers, refining the semiclassical energy landscape for quantum annealing.
2. Optimal Annealing Time: The presence of tunneling barriers facilitates the discovery of optimal annealing times for problem sizes involving more than 2000 qubits on the D-Wave 2000Q processor. The identified gadgets were critical in optimizing the annealing time, allowing for an effective TTS benchmarking.
3. Performance Comparison: The D-Wave device demonstrated a scaling advantage over simulated annealing in solving the provided instances but did not outperform discrete-time simulated quantum annealing (SQA), which displayed the best scaling results. The paper correlates SQA’s advantage with its ability to effectively traverse energy barriers similarly to quantum tunneling.
4. Temperature Considerations: The paper finds that the quantum annealer's sub-optimal high operational temperature diminishes its performance relative to SQA. It suggests that SQA’s success can be partially attributed to its lower operational temperatures in simulations.

Implications and Future Directions

The research provides insights into the potential of quantum annealers and emphasizes the importance of instance design in assessing quantum hardware's capabilities. Although the paper does not claim a complete quantum speedup, it lays the groundwork for further exploration into how specific problem constructs can be leveraged to maximize quantum annealers' performance.

Future work could explore ways to enhance quantum coherence in annealers or improve their error correction capabilities, potentially leading to a scenario where true quantum speedups can be consistently observed. Furthermore, understanding and refining how quantum annealers interact with tailored problem instances might inform the development of more sophisticated quantum algorithms, which could eventually see broader applications in real-world scenarios.