DLAU: A Scalable Deep Learning Accelerator Unit on FPGA (1605.06894v1)

Abstract: As the emerging field of machine learning, deep learning shows excellent ability in solving complex learning problems. However, the size of the networks becomes increasingly large scale due to the demands of the practical applications, which poses significant challenge to construct a high performance implementations of deep learning neural networks. In order to improve the performance as well to maintain the low power cost, in this paper we design DLAU, which is a scalable accelerator architecture for large-scale deep learning networks using FPGA as the hardware prototype. The DLAU accelerator employs three pipelined processing units to improve the throughput and utilizes tile techniques to explore locality for deep learning applications. Experimental results on the state-of-the-art Xilinx FPGA board demonstrate that the DLAU accelerator is able to achieve up to 36.1x speedup comparing to the Intel Core2 processors, with the power consumption at 234mW.

• The paper introduces a novel FPGA-based accelerator that efficiently scales deep learning models via tiled and pipelined processing.
• It employs specialized units for matrix multiplication, partial sum accumulation, and activation to optimize throughput and resource usage.
• Performance benchmarks reveal up to 36.1x speedup at a 256x256 network size with only 234mW power consumption, ideal for energy-constrained applications.

An Analysis of "DLAU: A Scalable Deep Learning Accelerator Unit on FPGA"

The paper entitled "DLAU: A Scalable Deep Learning Accelerator Unit on FPGA" presents a comprehensive exploration of a specialized hardware architecture designed to accelerate deep learning computations utilizing FPGA technology. As the demand for more intricate deep learning models increases, the paper offers a methodical approach to enhance the performance of these models while maintaining low power consumption. The DLAU architecture is crafted to provide significant improvements over previous implementations by leveraging FPGA capabilities and utilizing innovative techniques to partition data effectively.

Key Features and Architecture

The authors introduce DLAU as a novel deep learning accelerator unit that is adaptable and scalable for various neural network sizes. The architecture efficiently implements large-scale network models by employing tiled data processing and pipelined processing units. The primary components of the DLAU include the Tiled Matrix Multiplication Unit (TMMU), Part Sum Accumulation Unit (PSAU), and Activation Function Acceleration Unit (AFAU). These units are configured to work in tandem, exploiting a stream-like data passing methodology to ensure optimal computational throughput.

Key features of the DLAU prototype include:

• Tile Techniques: This technique allows for the partitioning of large input datasets into smaller, manageable tiles, making it feasible to compute across different machine learning applications without exceeding resource capacities.
• Pipelined Architecture: The pipeline design of the DLAU ensures that each processing step (multiplication, accumulation, and activation) can be executed concurrently, achieving high throughput and reducing latency.
• Scalability: The architecture can accommodate the execution of a variety of deep learning models such as CNNs and DNNs, providing flexibility in application-specific configurations.

Performance Evaluation

The paper provides compelling numerical results, highlighting the performance improvements gained via the DLAU accelerator. The authors implemented DLAU on a Xilinx Zynq Zedboard and benchmarked it against an Intel Core2 processor. The paper reports a speedup of up to 36.1x at a 256x256 network size, demonstrating its computational efficiency. Additionally, the power consumption of DLAU is remarkably low at 234mW, showcasing its suitability for energy-constrained environments.

Table \ref{comparison} in the paper compares DLAU with other implementations, such as DianNao and FPGA-based accelerators, indicating that while DianNao achieves higher speedup, the FPGA-based DLAU offers greater adaptability for varying network sizes. Analyzing these metrics, the DLAU holds significant potential in scenarios where scalability and power efficiency outweigh raw computational speed.

Resource Utilization and Implications

Resource utilization analysis reveals that DLAU makes efficient use of available FPGA resources, including BRAMs, DSPs, FFs, and LUTs. The use of tile techniques minimizes on-chip memory requirements, allowing the DLAU to support larger models without requiring excessive hardware. This efficient resource management implies potential applications in real-time systems and other constrained environments where flexibility and power consumption are critical considerations.

The implications of the DLAU architecture extend beyond immediate performance gains. It offers a framework for future research in designing more generalized accelerator architectures that can adapt to evolving deep learning paradigms. Moreover, it opens up possibilities for deploying scalable accelerators in edge computing environments where resource constraints often limit the feasibility of traditional acceleration hardware.

Future Research Directions

The authors acknowledge ongoing challenges, such as optimizing memory access patterns and further refining the weight matrix organization. Future investigations might include exploring hybrid FPGA-GPU acceleration techniques to combine the strengths of both platforms. Moreover, conducting extensive real-world application testing could refine the practical applicability and robustness of the DLAU system.

In conclusion, this paper contributes significantly to the academic discourse on FPGA-based acceleration of deep learning workloads. Its methodological approach to leveraging FPGA's configurability indicates tangible advancements towards more flexible, scalable, and energy-efficient deep learning solutions. As deep learning models continue to grow in complexity and scale, architectures like DLAU will be foundational in meeting computational and environmental demands.