Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits (1509.05081v2)

Abstract: We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum(SFQ) digital circuits with very large scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where 'ee' denotes the process is tuned for energy efficient SFQ circuits. The former has eight superconducting layers with 0.5 {\mu}m minimum feature size and a 2 {\Omega}/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNx layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tc < 2 K) MoNx layer with lower nitrogen content is used for 6 {\Omega}/sq planar resistors for shunting and biasing of Josephson junctions. Another resistive layer is added to form interlayer, sandwich-type resistors of m{\Omega} range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlOx-Al/Nb JJs with critical current density, Jc of 100 {\mu}A/{\mu}m^2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, critical current and Jc targeting, effect of hydrogen dissolved in Nb, MoNx properties for the resistor layer and for high kinetic inductance layer, technology of m{\Omega}-range resistors.

Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

The paper by Tolpygo et al. addresses critical advancements in the fabrication processes for superconducting Very Large Scale Integration (VLSI) circuits, focusing on two specific superconducting digital circuit technology nodes developed at MIT Lincoln Laboratory—SFQ4ee and SFQ5ee. These technologies leverage Single Flux Quantum (SFQ) digital circuits to potentially outperform conventional CMOS circuits in terms of speed and energy efficiency.

Fabrication Process Overview

The SFQ4ee node comprises eight layers of niobium (Nb) with a minimum feature size of 0.5 µm. It also incorporates a 2 Ω/sq molybdenum (Mo) layer for circuit resistors, which is crucial for the shunting and biasing of Josephson Junctions (JJs). The technology stack employs Niobium/Aluminium oxide-Al/Nb JJs with a critical current density $J_c$ of 100 µA/µm².

The SFQ5ee node introduces several enhancements compared to SFQ4ee. It adds a ninth layer for superconducting circuits, utilizes a 6 Ω/sq molybdenum nitride (MoN$_x$) layer for resistors, and incorporates a novel film with high kinetic inductance placed below the first Nb layer to optimize bias inductors. These upgrades are motivated by the aim to reduce the disparity between superconducting and semiconductor electronics, improve process maturity, and enhance integration capacity by offering finer minimum feature sizes (down to 350 nm) and minimum via sizes (500 nm).

Key Results and Observations

• Josephson Junction Conductance: More than 80 wafers were fabricated to examine the tuning of critical current density and impacts of fabrication process variations. Conductance variations due to topography beneath the JJs, characterized by a less than 1% increase in conductance, were documented, indicating manageable variability for most practical applications.
• Impact of Hydrogen Contamination: Notably, the paper identifies hydrogen as a significant contaminant affecting JJ performance, leading to a 10% difference in conductance between hydrogen-contaminated and clean superconductor layers.
• High-Kinetic-Inductance Layer: By introducing a MoN$_x$ layer, the SFQ5ee node significantly enhances the inductive elements necessary for various SFQ circuits. These high-inductance elements hold the potential to improve biasing inductors in energy-efficient ERSFQ circuits.
• Planar Resistors and Milliohm-Range Resistors: The new process incorporates sandwich-type resistors with small resistive values to minimize magnetic flux trapping—a critical circuit reliability issue.

Implications and Future Work

The advancements presented in these fabrication processes signify a notable progression towards making superconducting electronics more competitive with well-established CMOS technologies. The SFQ4ee and SFQ5ee nodes demonstrate a potential reduction in the substantial gap between the current capabilities of superconducting circuits compared to their semiconductor counterparts, especially in high-performance computing applications.

Future developments will likely focus on scaling integration capabilities further, reducing contamination effects such as hydrogen ingress, and refining the stability and performance of JJs and associated SFQ circuit components.

The work lays a substantial foundation for both practical implications in superconductor VLSI technology and the theoretical understanding of fabrication processes, impacting fields such as quantum computing and low-temperature electronics. Although this paper specifically discusses SFQ circuits, the findings could guide future research and process development in adjacent areas of superconducting electronics.

Overall, the authors delineate a methodical approach to addressing the physical and material science challenges in advancing superconductor electronics, thereby charting a course for enhanced VLSI circuit design and fabrication.