Layout decomposition for triple patterning lithography (1402.2459v1)

Abstract: As minimum feature size and pitch spacing further decrease, triple patterning lithography (TPL) is a possible 193nm extension along the paradigm of double patterning lithography (DPL). However, there is very little study on TPL layout decomposition. In this paper, we show that TPL layout decomposition is a more difficult problem than that for DPL. We then propose a general integer linear programming formulation for TPL layout decomposition which can simultaneously minimize conflict and stitch numbers. Since ILP has very poor scalability, we propose three acceleration techniques without sacrificing solution quality: independent component computation, layout graph simplification, and bridge computation. For very dense layouts, even with these speedup techniques, ILP formulation may still be too slow. Therefore, we propose a novel vector programming formulation for TPL decomposition, and solve it through effective semidefinite programming (SDP) approximation. Experimental results show that the ILP with acceleration techniques can reduce 82% runtime compared to the baseline ILP. Using SDP based algorithm, the runtime can be further reduced by 42% with some tradeoff in the stitch number (reduced by 7%) and the conflict (9% more). However, for very dense layouts, SDP based algorithm can achieve 140x speed-up even compared with accelerated ILP.

• The paper formulates triple patterning lithography layout decomposition as an optimization problem, using integer linear programming (ILP) and semidefinite programming (SDP) to minimize color conflicts and stitches.
• Novel acceleration techniques for ILP reduced runtime by 82%, while an SDP approximation provided a 140x speedup for very dense layouts with minor quality tradeoff.
• These methodologies enhance scalability in lithographic processes, enabling smaller, more efficient circuits and advancing semiconductor manufacturing.

Overview of "Layout Decomposition for Triple Patterning Lithography"

The paper "Layout Decomposition for Triple Patterning Lithography" by Bei Yu et al. addresses the complexities involved in the design and optimization of layouts for triple patterning lithography (TPL). This research is positioned within the context of semiconductor manufacturing, where the scaling of feature sizes further demands advances in lithographic techniques, especially as the industry approaches the sub-22nm half-pitch. While double patterning lithography (DPL) has been extensively explored and adopted, TPL presents additional challenges and opportunities for refinement.

Problem Formulation and Approach

The central contribution of this work is its formulation of TPL layout decomposition as a complex optimization problem. This problem is characterized by the dual objectives of minimizing color conflicts and the number of stitches necessary during lithographic processing. The authors efficiently model this problem using integer linear programming (ILP) and introduce a series of novel acceleration techniques to improve the tractability of this approach.

Three primary acceleration techniques are introduced:

1. Independent Component Computation: Decomposing the layout graph into smaller independent subproblems to simplify the computation.
2. Layout Graph Simplification: Systematically reducing graph complexity by temporarily removing lower-degree nodes.
3. Bridges Computation: Identifying and using edge bridges to partition the graph into manageable components without increasing stitches.

For dense layouts where accelerated ILP remains computationally intensive, the authors propose an alternative vector programming formulation solved via semidefinite programming (SDP) approximation. The formulation relies on transforming discrete color assignments into continuous vector spaces, which can be efficiently approximated and subsequently mapped back to a feasible discrete solution.

Results and Implications

The experimental results demonstrate significant reductions in runtime when applying the proposed acceleration techniques to the ILP formulation, cutting computational time by approximately 82% for certain benchmarks while maintaining solution quality. In extreme cases where ILP struggles with rapidly increasing complexity, the SDP algorithm achieves a further 42% runtime reduction at a minor tradeoff in conflict minimization quality. Notably, for exceptionally dense layouts, the SDP approach offers a remarkable $140\times$ speedup, underscoring its potential utility in high-density designs.

The implications of this work are profound for both theoretical and practical aspects of lithographic design. Theoretically, the paper advances understanding in the computational complexities associated with multi-patterning and provides a robust foundation for further exploration into efficient solving techniques for NP-hard problems in layout decomposition. Practically, these methodologies enable improved scalability in lithographic processes, paving the way for advanced semiconductor manufacturing by facilitating smaller and more efficient TPL-compatible circuits.

Future Directions

Moving forward, there is considerable scope for refining these algorithms and exploring new heuristics to further optimize the tradeoffs between runtime efficiency and quality in layout decomposition. Additionally, integrating these methods into industrial-scale electronic design automation tools could accelerate their adoption and validate their efficacy across varied real-world scenarios in semiconductor fabrication. Furthermore, while this paper focuses on TPL, the outlined methodologies could extend to quadruple patterning and other advanced lithographic techniques as the industry evolves.

In conclusion, this paper makes a significant contribution to the field by rigorously formulating and solving the TPL layout decomposition problem, demonstrating both robust theoretical grounding and applicability to real-world lithographic design challenges.