From Block to Byte: Transforming PCIe SSDs with CXL Memory Protocol and Instruction Annotation (2506.15613v1)

Abstract: This paper explores how Compute Express Link (CXL) can transform PCIe-based block storage into a scalable, byte-addressable working memory. We address the challenges of adapting block storage to CXL's memory-centric model by emphasizing cacheability as a key enabler and advocating for Type 3 endpoint devices, referred to as CXL-SSDs. To validate our approach, we prototype a CXL-SSD on a custom FPGA platform and propose annotation mechanisms, Determinism and Bufferability, to enhance performance while preserving data persistency. Our simulation-based evaluation demonstrates that CXL-SSD achieves 10.9x better performance than PCIe-based memory expanders and further reduces latency by 5.4x with annotation enhancements. In workloads with high locality, CXL-SSD approaches DRAM-like performance due to efficient on-chip caching. This work highlights the feasibility of integrating block storage into CXL's ecosystem and provides a foundation for future memory-storage convergence.

• The paper demonstrates how integrating the CXL protocol transforms PCIe SSDs from block storage into cache-coherent, byte-addressable memory with up to 10.9x performance gains.
• The research employs FPGA prototypes and simulation models to validate that instruction annotations improve latency and data persistence in storage systems.
• The study highlights that bufferability and determinism annotations optimize data management, facilitating scalable and efficient heterogeneous computing environments.

Transforming PCIe SSDs with CXL Protocol

The paper "From Block to Byte: Transforming PCIe SSDs with CXL Memory Protocol and Instruction Annotation" offers an in-depth analysis of how Compute Express Link (CXL) protocol can transition PCIe-based block storage into a byte-addressable, scalable working memory. According to the researchers, CXL offers several advantages by enabling cacheability and facilitating the adoption of Type 3 endpoint devices, which are termed CXL-SSDs. These devices can leverage existing PCIe storage technologies to operate more like DRAM, thereby increasing the applicability and efficiency of such systems in data center environments.

Key Concepts and Methodologies

The paper first contextualizes the operational landscape of CXL within broader industry trends by contrasting it with existing interconnect technologies like Gen-Z and CCIX. CXL distinguishes itself through its open protocol design aimed at optimizing heterogeneous computing environments, making it suitable for extending the capabilities of CPUs, GPUs, FPGAs, and domain-specific ASICs. The inherent capability of CXL to incorporate memory disaggregation highlights its potential in pooling diverse memory types, including both DRAM and byte-addressable persistent memory.

PCIe-based block storage is primarily limited by its non-cacheable nature, which CXL addresses through cache coherence. Currently, standard PCIe semantics are inadequate for byte-addressability conversion due to lack of cache coherency, leading to latency issues that impede memory systems. CXL memorably advances this paradigm by embracing cache-coherent memory sharing capabilities, which is largely beneficial for transforming PCIe SSDs into memory expansion devices that perform byte-addressable operations.

Technical Evaluation

Researchers conducted a robust evaluation involving prototypical CXL-SSD and compared it with PCIe-based memory expanders. The paper demonstrates that CXL-SSD achieves a performance enhancement approximately 10.9 times greater than that of PCIe devices, and with the introduction of annotation mechanisms aimed at improving latency and preserving data persistence, this margin further increases by 5.4 times on average.

The paper leverages FPGA-based prototypes and simulation models for performance validation. Such simulations serve as key instruments in illustrating the practical advancements achieved by integrating CXL protocols over traditional storage paradigms. In scenarios demonstrating high workload locality, CXL-SSD performance approximates that of DRAM due to its caching mechanisms, indicating DRAM-like efficiency and potential for broader applicability.

Instruction Annotations and Their Implications

Two annotation mechanisms introduced in the paper—Bufferability and Determinism—play central roles in optimizing performance while maintaining data integrity. Bufferability determines the likelihood of a request being buffered within an internal DRAM to economize latency, whereas Determinism flags requests necessitating precise timing considerations to prevent delays. Together, these mechanisms enable more intelligent data management within memory expanders, potentially redefining performance benchmarks associated with conventional storage systems.

Storage Disaggregation Considerations

The discussion extends into storage disaggregation, contemplating systems where numerous hosts can share underlying storage resources through CXL switches and virtual hierarchies. While this approach enhances scalability, considerations must be made regarding bandwidth allocation and potential congestion, necessitating refined network designs.

Conclusion

This paper contributes valuable insights into the feasibility of integrating block storage into the modern cache-coherent ecosystem offered by CXL protocols. By leveraging cacheability and deploying strategic instruction annotations, PCIe SSDs stand to improve their performance metrics significantly, approaching levels associated with DRAM under the right conditions. Future research could benefit by further exploring use cases across various computational paradigms and refining virtualization approaches for more efficient disaggregated storage models.