The Effect of Trap Design on the Scalability of Trapped-Ion Quantum Technologies (2503.00218v2)

Abstract: To increase the power of a trapped ion quantum information processor, the qubit number, gate speed, and gate fidelity must all increase. All three of these parameters are influenced by the trapping field which in turn depends on the electrode geometry. Here we consider how the electrode geometry affects the radial trapping parameters: trap height, harmonicity, depth, and trap frequency. We introduce a simple multi-wafer geometry comprising a ground plane above a surface trap and compare the performance of this trap to a surface trap and a multi-wafer trap that is a miniaturized version of a linear Paul trap. We compare the voltage and frequency requirements needed to reach a desired radial trap frequency and find that the two multi-wafer trap designs provide significant improvements in expected power dissipation over the surface trap design in large part due to increased harmonicity. Finally, we consider the fabrication requirements and the path towards integration of the necessary optical control. This work provides a basis to optimize future trap designs with scalability in mind.