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Single-qubit gates with errors at the $10^{-7}$ level (2412.04421v3)

Published 5 Dec 2024 in quant-ph

Abstract: We report the achievement of single-qubit gates with sub-part-per-million error rates, in a trapped-ion ${43}$Ca${+}$ hyperfine clock qubit. We explore the speed/fidelity trade-off for gate times $4.4\leq t_{g}\leq35~\mu$s, and benchmark a minimum error per Clifford gate of $1.5(4) \times 10{-7}$. Calibration errors are suppressed to $< 10{-8}$, leaving qubit decoherence ($T_{2}\approx 70$ s), leakage, and measurement as the dominant error contributions. The ion is held above a microfabricated surface-electrode trap which incorporates a chip-integrated microwave resonator for electronic qubit control; the trap is operated at room temperature without magnetic shielding.

Summary

  • The paper demonstrates achieving single-qubit gate error rates as low as 1.5(4) x 10^-7 in a 43Ca+ trapped-ion system, setting a new performance benchmark for quantum gate fidelity.
  • High fidelity was achieved through a combination of precise iterative amplitude and frequency calibration techniques and characterization of dominant error sources like decoherence.
  • Achieving sub-part-per-million errors crucially reduces the qubit overhead required for fault-tolerant quantum error correction, advancing the feasibility of scalable quantum computers.

Overview of High-Fidelity Single-Qubit Gates in Trapped-Ion Systems

In the field of quantum information processing, achieving high-fidelity quantum logic operations is crucial for the development of fault-tolerant quantum computing architectures. This paper articulates advancements in reducing error rates in single-qubit operations to a sub-part-per-million level, specifically reaching error benchmarks as low as 1.5(4)×1071.5(4) \times 10^{-7} for single-qubit gates in a 43^{43}Ca+^{+} trapped-ion system. By doing so, the researchers demonstrate a path towards diminishing the qubit overhead needed for error correction, thus enhancing the feasibility of scalable quantum systems.

Experimental Setup and Methodology

The experimental setup incorporates a microfabricated surface-electrode ion trap with integrated microwave resonators designed for controlled electronic manipulation of a 43^{43}Ca+^{+} hyperfine clock qubit. Conducted at room temperature without additional magnetic shielding, this setup underscores the stability and precision of gate operations without reliance on expensive and complex apparatus. The qubits are manipulated using a sequence of Clifford gates, decomposed into ±π/2\pm \pi/2 pulses, and errors are quantified using the technique of randomised benchmarking (RB).

Error Analysis and Contributions

The researchers identify multiple sources of error contributing to gate fidelity loss, namely qubit decoherence, leakage, measurement inaccuracies, and technical noise sources such as amplitude fluctuations and microwave-induced ac Zeeman shifts. By interrogating these sources, they were able to predict a gate error rate in close agreement with experimentally measured values. The dominant error identified was decoherence, with a characteristic time constant T2=69(7)T_{2}^{**} = 69(7) s, measured through a combination of memory benchmarking and spin-echo Ramsey measurement.

Calibration Techniques

Central to achieving the reported fidelity was the development and application of precise calibration techniques for both amplitude and frequency. The team employed an iterative calibration procedure interleaved with benchmarking trials to minimize amplitude drift error to 9(7)×1099(7) \times 10^{-9}. Additionally, the frequency adjustments accounted for ac Zeeman shifts at the level of 9 Hz, further ensuring the functional integrity of the qubit gates within the margin of technical limitations such as amplitude resolution.

Implications and Future Directions

This paper sets a new performance benchmark for single-qubit gate fidelities in ion-trap systems, surpassing previous efforts by notable margins both in speed and error minimization. This achievement portends the potential reduction in resources required for quantum error correction, paving the way for more efficient quantum computational implementations. Moving forward, the primary challenges involve further minimizing decoherence under real-world conditions and addressing both technical and quantum state preparation inaccuracies. Possible extensions of this paper might encompass the application of similar techniques to other ion species and scaling to multi-qubit interactions with equally high fidelity.

In conclusion, the refinement of single-qubit gate operations to error levels orders of magnitude below threshold values crucially supports the broader pursuit of a fault-tolerant quantum computer. The results and methodologies presented herein demonstrate tangible progress, underpinning both practical quantum algorithm implementation and the continuing theoretical exploration in quantum error correction. As such, this work will likely influence ongoing and future developments in both quantum hardware design and quantum control protocol optimization.

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