ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package (2410.15985v1)

Abstract: The increasing complexity of real-time control algorithms and the trend toward 2.5D technology necessitate the development of scalable controllers for managing the complex, integrated operation of chiplets within 2.5D systems-in-package. These controllers must provide real-time computing capabilities and have chiplet-compatible IO interfaces for communication with the controlled components. This work introduces ControlPULPlet, a chiplet-compatible, real-time multi-core RISC-V controller, which is available as an open-source release. It includes a 32-bit CV32RT core for efficient interrupt handling and a specialized direct memory access (DMA) engine to automate periodic sensor readouts. A tightly-coupled programmable multi-core accelerator is integrated via a dedicated AXI4 port. A flexible AXI4-compatible die-to-die (D2D) link supports inter-chiplet communication in 2.5D systems and enables high-bandwidth transfers in traditional 2D monolithic setups. We designed and fabricated ControlPULPlet as a silicon prototype called Kairos using TSMC's 65nm CMOS technology. Kairos executes predictive control algorithms at up to 290 MHz while consuming just 30 mW of power. The D2D link requires only 16.5 kGE in physical area per channel, adding just 2.9% to the total system area. It supports off-die access with an energy efficiency of 1.3 pJ/b and achieves a peak duplex transfer rate of 51 Gb/s per second at 200 MHz.

• The paper introduces a multi-core RISC-V controller optimized for real-time control in 2.5D SiP systems with a 32-bit CV32RT core and programmable accelerator.
• It demonstrates efficient inter-chiplet communication via a novel AXI4-compatible D2D link, achieving up to 51.2 Gbps duplex peak transfer at 200 MHz.
• Experimental validation on the Kairos chip shows near 290 MHz peak operation at 30 mW, emphasizing scalability and low energy-per-bit performance.

ControlPULPlet: An Examination of a Multi-Core RISC-V Controller for 2.5D Systems

The paper introduces ControlPULPlet, a sophisticated RISC-V multi-core controller designed to address the evolving requirements of real-time control in 2.5D systems-in-package (SiP). The research presents a scalable solution reflecting trends towards higher complexity in control tasks and the shift towards chiplet technologies in processor design.

Key Architectural Insights

ControlPULPlet is architecturally advanced, focusing on real-time and deterministic performance, which is critical for modern multi-input multi-output (MIMO) control systems. The core architecture employs a 32-bit CV32RT RISC-V core optimized for rapid interrupt handling and a multi-core setup suitable for compute-intensive tasks. Notably, the platform incorporates a programmable multi-core accelerator (PMCA) connected via a high-speed AXI4 bus. This configuration supports a broad range of control algorithms, from traditional methods to more complex model predictive control (MPC) policies.

The introduction of a die-to-die (D2D) link signifies a critical advancement in the integration of chiplets. The D2D link, realized through a novel, flexible, AXI4-compatible interface, facilitates efficient inter-chiplet communications in 2.5D systems. This feature is essential considering that 2.5D integrations require lower latency and higher throughput across distributed components.

Experimental Demonstration: The Kairos Chip

The authors have substantiated their conceptual framework with a fabricated test chip, Kairos, using TSMC's 65nm CMOS technology. The experimental setup substantiates that the single-core demonstrator version can operate near a peak frequency of 290 MHz under a power constraint of 30 mW, offering substantial insights into the efficiency of the system design.

Through block parameter tuning and silicon evaluation, significant findings include the low energy-per-bit metric of 1.3 picojoules associated with the D2D link, which supplies up to 51.2 Gbps duplex peak transfer at 200 MHz, reinforcing the supposition of ControlPULPlet's capability to manage high-data-rate control environments while maintaining a lightweight silicon footprint.

Comparative Landscape and Implications

Comparative analysis shows that ControlPULPlet excels in specific domains where existing single-core and multi-core architectures fall short, particularly in facilitating chiplet-based systems and heterogenous integration. By addressing limitations in traditional MCM setups, this work opens potential pathways for deploying complex control algorithms in robust environments demanding both flexibility and real-time execution.

Practically, ControlPULPlet addresses integration challenges by offering a modular, scalable solution compatible with varying industrial applications, such as robotics and automotive systems, where reduced latency and deterministic execution are paramount.

Future Prospects

The paper's implications reveal promising prospects for further refinements and incorporation in diverse fields. Advances in enhanced inter-chiplet communication protocols could be explored to further alleviate synchronization burdens and improve the modularity and interoperability standards of such controllers in high-demand applications. On a theoretical front, continued developments in RISC-V architectures tailored towards SiP designs could significantly impact the broader AI and IoT ecosystems by propelling forward the capabilities of edge processing units.

In conclusion, ControlPULPlet represents a significant effort to bridge the gap between rising control complexity and emergent chiplet technologies, presenting a viable avenue for advancing real-time control systems and their embedded architectures. The open-source nature of the project has the potential to catalyze collaborative advancements and wide-scale adoption in real-time system design.

Through meticulous design and rigorous empirical validation, this paper contributes substantively to the discourse on multi-core RISC-V controllers and their integration into the future landscape of semiconductor technologies.