Switchboard: An Open-Source Framework for Modular Simulation of Large Hardware Systems (2407.20537v1)

Abstract: Scaling up hardware systems has become an important tactic for improving performance as Moore's law fades. Unfortunately, simulations of large hardware systems are often a design bottleneck due to slow throughput and long build times. In this article, we propose a solution targeting designs composed of modular blocks connected by latency-insensitive interfaces. Our approach is to construct the hardware simulation in a similar fashion as the design itself, using a prebuilt simulator for each block and connecting the simulators via fast shared-memory queues at runtime. This improves build time, because simulation scale-up simply involves running more instances of the prebuilt simulators. It also addresses simulation speed, because prebuilt simulators can run in parallel, without fine-grained synchronization or global barriers. We introduce a framework, Switchboard, that implements our approach, and discuss two applications, demonstrating its speed, scalability, and accuracy: (1) a web application where users can run fast simulations of chiplets on an interposer, and (2) a wafer-scale simulation of one million RISC-V cores distributed across thousands of cloud compute cores.

• The paper presents a modular simulation approach that reduces build times and alleviates bottlenecks by integrating prebuilt simulators with latency-insensitive interfaces.
• It achieves remarkable scalability with trials including one million RISC-V cores and interactive chiplet emulation demonstrating up to 8,900x speedup.
• The framework supports heterogeneous models, enabling efficient simulations across RTL, FPGA-emulated, and software-based components for diverse hardware designs.

Review of "Switchboard: An Open-Source Framework for Modular Simulation of Large Hardware Systems"

The paper "Switchboard: An Open-Source Framework for Modular Simulation of Large Hardware Systems" proposes a modular simulation approach for large hardware systems composed of modular blocks connected by latency-insensitive interfaces. This technique is particularly significant in the post-Moore's law era, where there is an imperative need to scale up hardware systems to enhance performance.

Framework Overview and Implementation

Switchboard leverages prebuilt simulations of modular blocks and connects them through a high-performance shared-memory queue. This modular approach not only simplifies the scaling up of simulations but also significantly reduces build times and alleviates simulation bottlenecks. Key aspects of Switchboard include:

1. Latency-Insensitive Interfaces: The approach focuses on hardware blocks communicating through interfaces that are insensitive to latency (e.g., AXI, TileLink). This decision ensures that simulations do not require fine-grained synchronization, improving efficiency.
2. Prebuilt Simulators: By using prebuilt simulators for each block, the framework allows quick assembly of larger systems, thus reducing the time-to-simulation considerably.
3. Shared-Memory Queues: The primary communication mechanism between simulators in Switchboard is a fast shared-memory queue. This allows distributed simulations to run in parallel without explicit cycle-by-cycle synchronization.
4. Heterogeneous Simulation: Switchboard supports simulations composed of various types of models, including RTL, FPGA-emulated, and software-based models. This flexibility is crucial for adapting the simulation framework to different types of hardware designs.

Applications and Evaluation

The authors have demonstrated Switchboard's capabilities through two distinct applications:

1. Interactive Chiplet Emulation via Web Application: In this application, users can interactively create hardware systems by selecting chiplets from a catalog and arranging them on a virtual substrate. The underlying simulations are powered by prebuilt simulator blocks, some of which are implemented on FPGAs for higher performance. This enables tasks such as booting Linux on a RISC-V CPU chiplet and performing machine learning inference on an ML accelerator chiplet, achieving notable performance improvements (up to 8,900x speedup over local RTL simulations).
2. Simulation of One Million RISC-V Cores: The framework was tested for large-scale simulation involving one million RISC-V cores distributed across cloud compute instances. This demonstration highlights Switchboard’s scalability and ability to handle extremely large simulations across widely distributed resources efficiently.

Performance and Scalability

Through empirical results, the paper provides evidence that Switchboard excels in both build time and simulation speed:

• Build Time: The paper notes significant reductions in build time compared to traditional parallel RTL simulations. The framework's modular nature allows users to circumvent the lengthy build processes associated with large monolithic simulations.
• Scalability: The evaluation showcases the framework’s capacity to scale up simulations using standard cloud resources efficiently. With meticulous use of fast shared-memory queues and latency-insensitive interfaces, Switchboard can simulate systems of enormous scale with reasonable accuracy.

Future Directions

The research implies multiple vectors for future work:

• Improvement in Mixed-Signal Support: Current work has started to integrate SPICE models, facilitating mixed-signal simulations within the same framework.
• Enhanced Performance Tuning: There is room for optimizing simulation rate controls to further enhance performance accuracy without sacrificing speed.
• Broader Applications: Expanding the use cases to more diverse hardware systems could demonstrate the full potential and flexibility of Switchboard in various industrial and academic scenarios.

Conclusion

The Switchboard framework provides a robust, efficient, and flexible solution for simulating large hardware systems in a modular manner. It excels in reducing build times and scaling simulations across large computing infrastructures, thereby addressing some of the challenges in current simulation techniques. The practical demonstrations affirm the framework’s applicability and performance robust across different use cases. The flexibility to support heterogeneous simulation models positions it as a significant tool for future hardware system simulations, especially as we venture further into the post-Moore's law era.