Papers
Topics
Authors
Recent
Gemini 2.5 Flash
Gemini 2.5 Flash
12 tokens/sec
GPT-4o
12 tokens/sec
Gemini 2.5 Pro Pro
41 tokens/sec
o3 Pro
5 tokens/sec
GPT-4.1 Pro
37 tokens/sec
DeepSeek R1 via Azure Pro
33 tokens/sec
2000 character limit reached

A Unified Framework for Automated Code Transformation and Pragma Insertion (2405.03058v6)

Published 5 May 2024 in cs.SE and cs.PL

Abstract: High-level synthesis, source-to-source compilers, and various Design Space Exploration techniques for pragma insertion have significantly improved the Quality of Results of generated designs. These tools offer benefits such as reduced development time and enhanced performance. However, achieving high-quality results often requires additional manual code transformations and tiling selections, which are typically performed separately or as pre-processing steps. Although DSE techniques enable code transformation upfront, the vastness of the search space often limits the exploration of all possible code transformations, making it challenging to determine which transformations are necessary. Additionally, ensuring correctness remains challenging, especially for complex transformations and optimizations. To tackle this obstacle, we first propose a comprehensive framework leveraging HLS compilers. Our system streamlines code transformation, pragma insertion, and tiles size selection for on-chip data caching through a unified optimization problem, aiming to enhance parallelization, particularly beneficial for computation-bound kernels. Them employing a novel Non-Linear Programming (NLP) approach, we simultaneously ascertain transformations, pragmas, and tile sizes, focusing on regular loop-based kernels. Our evaluation demonstrates that our framework adeptly identifies the appropriate transformations, including scenarios where no transformation is necessary, and inserts pragmas to achieve a favorable Quality of Results.

Definition Search Book Streamline Icon: https://streamlinehq.com
References (43)
  1. A Practical Automatic Polyhedral Parallelizer and Locality Optimizer. In Proceedings of the 29th ACM SIGPLAN Conference on Programming Language Design and Implementation (Tucson, AZ, USA) (PLDI ’08). Association for Computing Machinery, New York, NY, USA, 101–113. https://doi.org/10.1145/1375581.1375595
  2. Allo: A Programming Model for Composable Accelerator Design. Proc. ACM Program. Lang. 8, PLDI, Article 171 (jun 2024). https://doi.org/10.1145/3656401
  3. Young-kyu Choi and Jason Cong. 2018. HLS-Based Optimization and Design Space Exploration for Applications with Variable Loop Bounds. In 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 1–8. https://doi.org/10.1145/3240765.3240815
  4. High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, 4 (2011), 473–491. https://doi.org/10.1109/TCAD.2011.2110592
  5. Lattice-Traversing Design Space Exploration for High Level Synthesis. In 2018 IEEE 36th International Conference on Computer Design (ICCD). 210–217. https://doi.org/10.1109/ICCD.2018.00040
  6. PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow. IEEE Trans. Comput. 70, 12 (2021), 2015–2028. https://doi.org/10.1109/TC.2021.3123465
  7. Intel. 2024. Intel. https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/hls-compiler.html
  8. HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. In Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (Seaside, CA, USA) (FPGA ’19). Association for Computing Machinery, New York, NY, USA, 242–251. https://doi.org/10.1145/3289602.3293910
  9. HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration. In Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (Seaside, CA, USA) (FPGA ’20). Association for Computing Machinery, New York, NY, USA, 51–57. https://doi.org/10.1145/3373087.3375320
  10. Throughput optimization for high-level synthesis using resource constraints. In Int. Workshop on Polyhedral Compilation Techniques (IMPACT’14).
  11. Analytical characterization and design space exploration for optimization of CNNs. In Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (Virtual, USA) (ASPLOS ’21). Association for Computing Machinery, New York, NY, USA, 928–942. https://doi.org/10.1145/3445814.3446759
  12. Hung-Yi Liu and Luca P. Carloni. 2013. On learning-based methods for design-space exploration with High-Level Synthesis. In 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC). 1–7.
  13. Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS. In 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines. 159–162. https://doi.org/10.1109/FCCM.2015.31
  14. Polyhedral-based dynamic loop pipelining for high-level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 9 (2017), 1802–1815.
  15. Loop splitting for efficient pipelining in high-level synthesis. In 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 72–79.
  16. Tile size selection for optimized memory reuse in high-level synthesis. In 2017 27th International Conference on Field Programmable Logic and Applications (FPL). 1–8. https://doi.org/10.23919/FPL.2017.8056810
  17. Anushree Mahapatra and Benjamin Carrion Schafer. 2014. Machine-learning based simulated annealer method for high level synthesis design space exploration. In Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn). 1–6. https://doi.org/10.1109/ESLsyn.2014.6850383
  18. Microchip. 2023. SmartHLS Compiler Software. https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/smarthls-compiler
  19. PoCC [n. d.]. PoCC, the Polyhedral Compiler Collection 1.3. http://pocc.sourceforge.net
  20. PolyBench [n. d.]. PolyBench/C 4.2.1. http://polybench.sourceforge.net
  21. Polybench [n. d.]. PolyBench/C: the Polyhedral Benchmark suite. http://tinyurl.com/m7ztgex.
  22. Polyhedral-Based Data Reuse Optimization for Configurable Computing. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (Monterey, California, USA) (FPGA ’13). Association for Computing Machinery, New York, NY, USA, 29–38. https://doi.org/10.1145/2435264.2435273
  23. Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach. In Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (Monterey,CA,USA) (FPGA ’24). Association for Computing Machinery, New York, NY, USA, 184. https://doi.org/10.1145/3626202.3637593
  24. Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach. arXiv (2024).
  25. N. V. Sahinidis. 2017. BARON 21.1.13: Global Optimization of Mixed-Integer Nonlinear Programs, User’s Manual.
  26. Siemens. 2023. Catapult High-Level Synthesis. https://eda.sw.siemens.com/en-US/ic/catapult-high-level-synthesis/
  27. Automated Accelerator Optimization Aided by Graph Neural Networks. In 2022 59th ACM/IEEE Design Automation Conference (DAC).
  28. Robust GNN-Based Representation Learning for HLS. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD). 1–9. https://doi.org/10.1109/ICCAD57390.2023.10323853
  29. AutoDSE: Enabling Software Programmers Design Efficient FPGA Accelerators. In The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (Virtual Event, USA) (FPGA ’21). Association for Computing Machinery, New York, NY, USA, 147. https://doi.org/10.1145/3431920.3439464
  30. M. Tawarmalani and N. V. Sahinidis. 2005. A polyhedral branch-and-cut approach to global optimization. Mathematical Programming 103 (2005), 225–249. Issue 2.
  31. Sven Verdoolaege. 2011. Counting affine calculator and applications. In First International Workshop on Polyhedral Compilation Techniques (IMPACT’11), Chamonix, France.
  32. Polyhedral parallel code generation for CUDA. ACM Trans. Archit. Code Optim. 9, 4, Article 54 (jan 2013), 23 pages. https://doi.org/10.1145/2400682.2400713
  33. IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 42, 3 (2023), 900–913. https://doi.org/10.1109/TCAD.2022.3185540
  34. AMD Xilinx. 2023.2. Vitis. https://www.xilinx.com/products/design-tools/vitis.html
  35. AMD Xilinx. 2024. Merlin. https://github.com/Xilinx/merlin-compiler
  36. HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1 (La Jolla,CA,USA) (ASPLOS ’24). Association for Computing Machinery, New York, NY, USA, 215–230. https://doi.org/10.1145/3617232.3624850
  37. ScaleHLS: A Scalable High-Level Synthesis Framework with Multi-Level Transformations and Optimizations: Invited. In Proceedings of the 59th ACM/IEEE Design Automation Conference (San Francisco, California) (DAC ’22). Association for Computing Machinery, New York, NY, USA, 1355–1358. https://doi.org/10.1145/3489517.3530631
  38. S2FA: An Accelerator Automation Framework for Heterogeneous Computing in Datacenters. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC). 1–6. https://doi.org/10.1109/DAC.2018.8465827
  39. AutoPilot: A Platform-Based ESL Synthesis System. Springer Netherlands, Dordrecht, 99–112. https://doi.org/10.1007/978-1-4020-8588-8_6
  40. COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 430–437. https://doi.org/10.1109/ICCAD.2017.8203809
  41. Ruizhe Zhao and Jianyi Cheng. 2021. Phism: Polyhedral High-Level Synthesis in MLIR. arXiv preprint arXiv:2103.15103 (2021).
  42. POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. arXiv (2022).
  43. Lin-Analyzer: A high-level performance analysis tool for FPGA-based accelerators. In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC). 1–6. https://doi.org/10.1145/2897937.2898040
Citations (1)
View on Semantic Scholar

Summary

We haven't generated a summary for this paper yet.

Ai Sparkles Streamline Icon: https://streamlinehq.com Summarize Now