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DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands (2405.02499v1)

Published 3 May 2024 in cs.CR and cs.AR

Abstract: The demand for precise information on DRAM microarchitectures and error characteristics has surged, driven by the need to explore processing in memory, enhance reliability, and mitigate security vulnerability. Nonetheless, DRAM manufacturers have disclosed only a limited amount of information, making it difficult to find specific information on their DRAM microarchitectures. This paper addresses this gap by presenting more rigorous findings on the microarchitectures of commodity DRAM chips and their impacts on the characteristics of activate-induced bitflips (AIBs), such as RowHammer and RowPress. The previous studies have also attempted to understand the DRAM microarchitectures and associated behaviors, but we have found some of their results to be misled by inaccurate address mapping and internal data swizzling, or lack of a deeper understanding of the modern DRAM cell structure. For accurate and efficient reverse-engineering, we use three tools: AIBs, retention time test, and RowCopy, which can be cross-validated. With these three tools, we first take a macroscopic view of modern DRAM chips to uncover the size, structure, and operation of their subarrays, memory array tiles (MATs), and rows. Then, we analyze AIB characteristics based on the microscopic view of the DRAM microarchitecture, such as 6F2 cell layout, through which we rectify misunderstandings regarding AIBs and discover a new data pattern that accelerates AIBs. Lastly, based on our findings at both macroscopic and microscopic levels, we identify previously unknown AIB vulnerabilities and propose a simple yet effective protection solution.

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References (85)
  1. M. V. Beigi, Y. Cao, S. Gurumurthi, C. Recchia, A. Walton, and V. Sridharan, “A Systematic Study of DDR4 DRAM Faults in the Field,” in HPCA, 2023.
  2. Y. Cohen, K. S. Tharayil, A. Haenel, D. Genkin, A. D. Keromytis, Y. Oren, and Y. Yarom, “HammerScope: Observing DRAM Power Consumption Using Rowhammer,” in Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security, 2022.
  3. L. Cojocar, J. Kim, M. Patel, L. Tsai, S. Saroiu, A. Wolman, and O. Mutlu, “Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers,” in 2020 IEEE Symposium on Security and Privacy (SP), 2020.
  4. L. Cojocar, K. Loughlin, S. Saroiu, B. Kasikci, and A. Wolman, “mFIT: A Bump-in-the-Wire Tool for Plug-and-Play Analysis of Rowhammer Susceptibility Factors,” Technical Report-Microsoft Research, 2021.
  5. L. Cojocar, K. Razavi, C. Giuffrida, and H. Bos, “Exploiting Correcting Codes: On the Effectiveness of ECC Memory Against Rowhammer Attacks,” in 2019 IEEE Symposium on Security and Privacy (SP), 2019.
  6. V. Costan and S. Devadas, “Intel SGX Explained,” Cryptology ePrint Archive, 2016.
  7. F. de Ridder, P. Frigo, E. Vannacci, H. Bos, C. Giuffrida, and K. Razavi, “SMASH: Synchronized Many-sided Rowhammer Attacks from JavaScript,” in 30th USENIX Security Symposium, 2021.
  8. A. Fakhrzadehgan, Y. N. Patt, P. J. Nair, and M. K. Qureshi, “SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection,” in HPCA, 2022.
  9. P. Frigo, E. Vannacc, H. Hassan, V. Van Der Veen, O. Mutlu, C. Giuffrida, H. Bos, and K. Razavi, “TRRespass: Exploiting the Many Sides of Target Row Refresh,” in 2020 IEEE Symposium on Security and Privacy (SP), 2020.
  10. F. Gao, G. Tziantzioulis, and D. Wentzlaff, “ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs,” in MICRO, 2019, p. 100–113.
  11. F. Gao, G. Tziantzioulis, and D. Wentzlaff, “FracDRAM: Fractional Values in Off-the-Shelf DRAM,” in MICRO, 2022.
  12. S. K. Gautam, S. K. Manhas, A. Kumar, and M. Pakala, “Mitigating the Passing Word Line Induced Soft Errors in Saddle Fin DRAM,” IEEE Transactions on Electron Devices, vol. 67, no. 4, pp. 1902–1905, 2020.
  13. H. Hassan, Y. C. Tugrul, J. S. Kim, V. Van der Veen, K. Razavi, and O. Mutlu, “Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications,” in MICRO, 2021.
  14. H. Hassan, N. Vijaykumar, S. Khan, S. Ghose, K. Chang, G. Pekhimenko, D. Lee, O. Ergin, and O. Mutlu, “SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies,” in HPCA, 2017.
  15. S. Hong, D. Kim, J. Lee, R. Oh, C. Yoo, S. Hwang, and J. Lee, “DSAC: Low-Cost Rowhammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm,” arXiv preprint arXiv:2302.03591, 2023.
  16. JEDEC, “High Bandwidth Memory DRAM(HBM1,HBM2),” 2015.
  17. JEDEC, “DDR4 SDRAM Standard,” 2017.
  18. JEDEC, “DDR4 SDRAM Registered DIMM Design Specification,” 2019.
  19. JEDEC, “DDR5 SDRAM Standard,” 2022.
  20. JEDEC, “DDR4 Registering Clock Driver (DDR4RCD02),” 2023.
  21. S. Ji, Y. Ko, S. Oh, and J. Kim, “Pinpoint Rowhammer: Suppressing Unwanted Bit Flips on Rowhammer Attacks,” in Proceedings of the 2019 ACM Asia Conference on Computer and Communications Security, 2019.
  22. J. Jung and M. Erez, “Predicting Future-System Reliability with a Component-Level DRAM Fault Model,” in MICRO, 2023, pp. 944–956.
  23. D. Kaplan, J. Powell, and T. Woller, “AMD Memory Encryption,” White paper, 2016.
  24. J. S. Kim, M. Patel, A. G. Yağlıkçı, H. Hassan, R. Azizi, L. Orosa, and O. Mutlu, “Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques,” in ISCA, 2020.
  25. J.-Y. Kim, M.-G. Kang, J.-Y. Lee, and B.-H. Cho, “Semiconductor Memory Device Having Dummy Bit Line,” 2015, uS Patent 9,147,440.
  26. M. J. Kim, J. Park, Y. Park, W. Doh, N. Kim, T. J. Ham, J. W. Lee, and J. Ahn, “Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh,” in HPCA, 2022, pp. 1156–1169.
  27. M. J. Kim, M. Wi, J. Park, S. Ko, J. Choi, H. Nam, N. S. Kim, J. Ahn, and E. Lee, “How to Kill the Second Bird with One ECC: The Pursuit of Row Hammer Resilient DRAM,” in MICRO, 2023.
  28. Y. Kim, R. Daly, J. Kim, C. Fallin, J. H. Lee, D. Lee, C. Wilkerson, K. Lai, and O. Mutlu, “Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors,” in ISCA, 2014.
  29. A. Kwong, D. Genkin, D. Gruss, and Y. Yarom, “RAMBleed: Reading Bits in Memory Without Accessing Them,” in 2020 IEEE Symposium on Security and Privacy (SP), 2020.
  30. D. Lee, S. Khan, L. Subramanian, S. Ghose, R. Ausavarungnirun, G. Pekhimenko, V. Seshadri, and O. Mutlu, “Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms,” Proceedings of the ACM on Measurement and Analysis of Computing Systems, 2017.
  31. E. Lee, I. Kang, S. Lee, G. E. Suh, and J. Ahn, “TWiCe: Preventing Row-hammering by Exploiting Time Window Counters,” in ISCA, 2019, pp. 385–396.
  32. S. Lee, K. Kim, S. Oh, J. Park, G. Hong, D. Ka, K. Hwang, J. Park, K. Kang, J. Kim, J. Jeon, N. Kim, Y. Kwon, K. Vladimir, W. Shin, J. Won, M. Lee, H. Joo, H. Choi, J. Lee, D. Ko, Y. Jun, K. Cho, I. Kim, C. Song, C. Jeong, D. Kwon, J. Jang, I. Park, J. Chun, and J. Cho, “A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications,” in 2022 IEEE International Solid-State Circuits Conference (ISSCC), vol. 65, 2022, pp. 1–3.
  33. S. Lee, S.-h. Kang, J. Lee, H. Kim, E. Lee, S. Seo, H. Yoon, S. Lee, K. Lim, H. Shin, J. Kim, O. Seongil, A. Iyer, D. Wang, K. Sohn, and N. S. Kim, “Hardware Architecture and Software Stack for PIM based on Commercial DRAM Technology: Industrial Product,” in ISCA, 2021.
  34. K.-N. Lim, W.-J. Jang, H.-S. Won, K.-Y. Lee, H. Kim, D.-W. Kim, M.-H. Cho, S.-L. Kim, J.-H. Kang, K.-W. Park, and B.-T. Jeong, “A 1.2 V 23nm 6F2 4Gb DDR3 SDRAM with Local-bitline Sense Amplifier, Hybrid LIO Sense Amplifier and Dummy-less Array Architecture,” in ISSCC, 2012.
  35. J. Liu, B. Jaiyen, Y. Kim, C. Wilkerson, and O. Mutlu, “An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms,” in ISCA, 2013.
  36. K. Loughlin, J. Rosenblum, S. Saroiu, A. Wolman, D. Skarlatos, and B. Kasikci, “Siloz: Leveraging DRAM Isolation Domains to Prevent Inter-VM Rowhammer,” in Proceedings of the 29th Symposium on Operating Systems Principles, 2023.
  37. K. Loughlin, S. Saroiu, A. Wolman, and B. Kasikci, “Stop! Hammer Time: Rethinking Our Approach to Rowhammer Mitigations,” in Proceedings of the Workshop on Hot Topics in Operating Systems, 2021.
  38. H. Luo, A. Olgun, A. G. Yağlıkçı, Y. C. Tuğrul, S. Rhyner, M. B. Cavlak, J. Lindegger, M. Sadrosadati, and O. Mutlu, “RowPress: Amplifying Read Disturbance in Modern DRAM Chips,” in ISCA, 2023.
  39. M. Marazzi, P. Jattke, F. Solt, and K. Razavi, “ProTRR: Principled yet Optimal In-DRAM Target Row Refresh,” in 2022 IEEE Symposium on Security and Privacy (SP), 2022.
  40. M. Marazzi, T. Sachsenweger, F. Solt, P. Zeng, K. Takashi, M. Yarema, and K. Razavi, “HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifiers with IC Imaging,” in ISCA, Jul. 2024.
  41. J. Meza, Q. Wu, S. Kumar, and O. Mutlu, “Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field,” in 2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2015, pp. 415–426.
  42. Micron, “DDR4 SDRAM RDIMM MTA36ASF4G72PZ – 32GB,” 2014.
  43. Micron, “DDR4 SDRAM RDIMM MTA18ASF2G72PZ – 16GB,” 2015.
  44. C. P. Mozak, “Suppressing Power Supply Noise Using Data Scrambling in Double Data Rate Memory Systems,” 2011, US Patent 7,945,050 B2.
  45. H. Nam, S. Baek, M. Wi, M. J. Kim, J. Park, C. Song, N. S. Kim, and J. H. Ahn, “X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands,” IEEE Comput. Archit. Lett., vol. 22, no. 2, pp. 89–92, 2023.
  46. A. Olgun, H. Hassan, A. G. Yağlıkçı, Y. C. Tuğrul, L. Orosa, H. Luo, M. Patel, O. Ergin, and O. Mutlu, “DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023.
  47. A. Olgun, M. Osseiran, A. G. Yaglikci, Y. C. Tugrul, H. Luo, S. Rhyner, B. Salami, J. G. Luna, and O. Mutlu, “Understanding Read Disturbance in High Bandwidth Memory: An Experimental Analysis of Real HBM2 DRAM Chips,” arXiv preprint arXiv:2310.14665, 2023.
  48. L. Orosa, U. Rührmair, A. G. Yaglikci, H. Luo, A. Olgun, P. Jattke, M. Patel, J. Kim, K. Razavi, and O. Mutlu, “SpyHammer: Using RowHammer to Remotely Spy on Temperature,” arXiv preprint arXiv:2210.04084, 2023.
  49. L. Orosa, A. G. Yaglikci, H. Luo, A. Olgun, J. Park, H. Hassan, M. Patel, J. S. Kim, and O. Mutlu, “A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses,” in MICRO, 2021.
  50. J. Park, B. Kim, S. Yun, E. Lee, M. Rhu, and J. Ahn, “TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory,” in MICRO, 2021.
  51. S.-W. Park, S.-J. Hong, J.-W. Kim, J.-G. Jeong, K.-D. Yoo, S.-C. Moon, H.-C. Sohn, N.-J. Kwak, Y.-S. Cho, S.-J. Baek, H.-S. Park, H. G. Yoon, B.-H. Lee, J.-S. Kim, S.-H. Hwang, L.-H. Lee, H.-J. Cho, S. Y. Cho, C.-O. Chung, K.-O. Kim, M.-S. Yoo, S.-A. Jang, S.-D. Lee, and S.-W. Chung, “Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology,” in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 2006, pp. 32–33.
  52. Y. Park, W. Kwon, E. Lee, T. J. Ham, J. Ahn, and J. W. Lee, “Graphene: Strong yet Lightweight Row Hammer Protection,” in MICRO, 2020, pp. 1–13.
  53. M. Patel, G. F. de Oliveira, and O. Mutlu, “HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes,” in MICRO, 2021.
  54. M. Patel, J. S. Kim, T. Shahroodi, H. Hassan, and O. Mutlu, “Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics,” in MICRO, 2020.
  55. Rambus, “DRAM Power Model,” 2010. [Online]. Available: https://www.rambus.com/energy
  56. K. Razavi, B. Gras, E. Bosman, B. Preneel, C. Giuffrida, and H. Bos, “Flip Feng Shui: Hammering a Needle in the Software Stack,” in 25th USENIX Security Symposium (USENIX Security 16), 2016.
  57. S.-W. Ryu, K. Min, J. Shin, H. Kwon, D. Nam, T. Oh, T.-S. Jang, M. Yoo, Y. Kim, and S. Hong, “Overcoming the Reliability Limitation in the Ultimately Scaled DRAM Using Silicon Migration Technique by Hydrogen Annealing,” in IEEE International Electron Devices Meeting (IEDM), 2017, pp. 21–6.
  58. G. Saileshwar, P. J. Nair, P. Ramrakhyani, W. Elsasser, and M. K. Qureshi, “SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories,” in HPCA, 2018.
  59. G. Saileshwar, B. Wang, M. Qureshi, and P. J. Nair, “Randomized Row-Swap: Mitigating Row Hammer by Breaking Spatial Correlation between Aggressor and Victim Rows,” in ASPLOS, 2022.
  60. S. Saroiu, A. Wolman, and L. Cojocar, “The Price of Secrecy: How Hiding Internal DRAM Topologies Hurts Rowhammer Defenses,” in 2022 IEEE International Reliability Physics Symposium (IRPS), 2022.
  61. V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, P. B. Gibbons, M. A. Kozuch, and T. C. Mowry, “RowClone: Fast and Energy-Efficient in-DRAM Bulk Data Copy and Initialization,” in MICRO, 2013.
  62. V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M. A. Kozuch, O. Mutlu, P. B. Gibbons, and T. C. Mowry, “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” in MICRO, 2017, pp. 273–287.
  63. S. M. Seyedzadeh, D. Kline Jr, A. K. Jones, and R. Melhem, “Mitigating Bitline Crosstalk Noise in DRAM Memories,” in Proceedings of the International Symposium on Memory Systems, 2017.
  64. T. Siddiqua, V. Sridharan, S. E. Raasch, N. DeBardeleben, K. B. Ferreira, S. Levy, E. Baseman, and Q. Guan, “Lifetime Memory Reliability Data from the Field,” in 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).   IEEE, 2017, pp. 1–6.
  65. Y. H. Son, S. Lee, S. O, S. Kwon, N. S. Kim, and J. Ahn, “CiDRA: A Cache-inspired DRAM Resilience Architecture,” in HPCA, 2015.
  66. V. Sridharan, N. DeBardeleben, S. Blanchard, K. B. Ferreira, J. Stearley, J. Shalf, and S. Gurumurthi, “Memory Errors in Modern Systems: The Good, The Bad, and The Ugly,” in ASPLOS, 2015.
  67. V. Sridharan, J. Stearley, N. DeBardeleben, S. Blanchard, and S. Gurumurthi, “Feng Shui of supercomputer memory positional effects in DRAM and SRAM faults,” in SC ’13: Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, 2013, pp. 1–11.
  68. T. Takahashi, T. Sekiguchi, R. Takemura, S. Narui, H. Fujisawa, S. Miyatake, M. Morino, K. Arai, S. Yamada, S. Shukuri, M. Nakamura, Y. Tadaki, K. Kajigaya, K. Kimura, and K. Itoh, “A Multigigabit DRAM Technology With 6F2superscript6F2\text{6F}^{\text{2}}6F start_POSTSUPERSCRIPT 2 end_POSTSUPERSCRIPT Open-Bitline Cell, Distributed Overdriven Sensing, and Stacked-Flash Fuse,” IEEE Journal of Solid-State Circuits, vol. 36, no. 11, pp. 1721–1727, 2001.
  69. A. N. Udipi, N. Muralimanohar, N. Chatterjee, R. Balasubramonian, A. Davis, and N. P. Jouppi, “Rethinking DRAM Design and Organization for Energy-constrained Multi-cores,” in ISCA, 2010, p. 175–186.
  70. A. J. Van De Goor and I. Schanstra, “Address and Data Scrambling: Causes and Impact on Memory Tests,” in Proceedings First IEEE International Workshop on Electronic Design, Test and Applications, 2002.
  71. V. Van Der Veen, Y. Fratantonio, M. Lindorfer, D. Gruss, C. Maurice, G. Vigna, H. Bos, K. Razavi, and C. Giuffrida, “Drammer: Deterministic Rowhammer Attacks on Mobile Platforms,” in Proceedings of the 2016 ACM SIGSAC conference on computer and communications security, 2016.
  72. A. J. Walker, S. Lee, and D. Beery, “On DRAM Rowhammer and the Physics of Insecurity,” IEEE Transactions on Electron Devices, vol. 68, no. 4, pp. 1400–1410, 2021.
  73. M. Wi, J. Park, S. Ko, M. J. Kim, N. S. Kim, E. Lee, and J. Ahn, “SHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling,” in HPCA, 2023.
  74. J. Woo, G. Saileshwar, and P. J. Nair, “Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems,” in HPCA, 2023.
  75. S. C. Woo, W. Elasasser, M. Hamburg, E. Linstadt, M. R. Miller, T. Song, and J. Tringali, “RAMPART: RowHammer Mitigation and Repair for Server Memory Systems,” in 9th International Symposium on Memory Systems, 2023.
  76. X.-C. Wu, T. Sherwood, F. T. Chong, and Y. Li, “Protecting Page Tables from RowHammer Attacks using Monotonic Pointers in DRAM True-Cells,” in ASPLOS, 2019.
  77. A. Xilinx, “Alveo U200 FPGA Board.” [Online]. Available: https://www.xilinx.com/products/boards-and-kits/alveo/u200.html
  78. A. Xilinx, “Alveo U280 FPGA Board.” [Online]. Available: https://www.xilinx.com/products/boards-and-kits/alveo/u280.html
  79. A. Xilinx, “Supercharge Your AI and Database Applications with Xilinx’s HBM-Enabled UltraScale+ Devices Featuring Samsung HBM2,” 2019.
  80. A. G. Yağlıkçı, H. Luo, G. F. De Oliviera, A. Olgun, M. Patel, J. Park, H. Hassan, J. S. Kim, L. Orosa, and O. Mutlu, “Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices,” in 2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2022.
  81. A. G. Yağlikçi, A. Olgun, M. Patel, H. Luo, H. Hassan, L. Orosa, O. Ergin, and O. Mutlu, “HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips,” in MICRO, 2022.
  82. S. F. Yitbarek, M. T. Aga, R. Das, and T. Austin, “Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors,” in HPCA, 2017.
  83. M. S. Yoo, K. S. Choi, W. K. Sun, S. G. Choi, J. I. Kim, Y. I. Son, H.-G. Choi, T. K. Oh, Y. T. Hwang, Y. Chun, J. G. Jeong, S. K. Park, J. H. Choi, S. J. Hong, and S. Park, “Saddle-fin cell transistors with oxide etch rate control by using tilted ion implantation (TIS-Fin) for sub-50-nm DRAMs,” Feb 2010.
  84. T. Zhang, K. Chen, C. Xu, G. Sun, T. Wang, and Y. Xie, “Half-DRAM: A High-bandwidth and Low-power DRAM Architecture from the Rethinking of Fine-grained Activation,” in ISCA, 2014, pp. 349–360.
  85. L. Zhou, J. Li, Z. Qiao, P. Ren, Z. Sun, J. Wang, B. Wu, Z. Ji, R. Wang, K. Cao, and R. Huang, “Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation,” in 2023 IEEE International Reliability Physics Symposium (IRPS), 2023.
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Authors (8)
  1. Hwayong Nam (2 papers)
  2. Minbok Wi (3 papers)
  3. Michael Jaemin Kim (5 papers)
  4. Jaehyun Park (31 papers)
  5. Chihun Song (3 papers)
  6. Nam Sung Kim (30 papers)
  7. Jung Ho Ahn (21 papers)
  8. SeungMin Baek (6 papers)
Citations (1)
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