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DRAM-Profiler: An Experimental DRAM RowHammer Vulnerability Profiling Mechanism (2404.18396v1)

Published 29 Apr 2024 in cs.CR and cs.AR

Abstract: RowHammer stands out as a prominent example, potentially the pioneering one, showcasing how a failure mechanism at the circuit level can give rise to a significant and pervasive security vulnerability within systems. Prior research has approached RowHammer attacks within a static threat model framework. Nonetheless, it warrants consideration within a more nuanced and dynamic model. This paper presents a low-overhead DRAM RowHammer vulnerability profiling technique termed DRAM-Profiler, which utilizes innovative test vectors for categorizing memory cells into distinct security levels. The proposed test vectors intentionally weaken the spatial correlation between the aggressors and victim rows before an attack for evaluation, thus aiding designers in mitigating RowHammer vulnerabilities in the mapping phase. While there has been no previous research showcasing the impact of such profiling to our knowledge, our study methodically assesses 128 commercial DDR4 DRAM products. The results uncover the significant variability among chips from different manufacturers in the type and quantity of RowHammer attacks that can be exploited by adversaries.

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References (39)
  1. 2015. Apple, Inc. About the security content of mac efi security update 2015-001. https://support.apple.com/en-au/HT204934.
  2. 2015. HP, Inc. Hp moonshot component pack. https://support.hpe.com/hpsc/doc/public/display?docId=c04676483,May2015.
  3. 2020. JESD79-4C: DDR4 SDRAM Standard. https://www.xilinx.com/products/boards-and-kits/alveo.html
  4. 2021. Xilinx Inc., Xilinx Alveo U200 FPGA Board. https://www.xilinx.com/products/boards-and-kits/alveo.html
  5. Tanj Bennett et al. 2021. Panopticon: A complete in-dram rowhammer mitigation. In DRAMSec, Vol. 22. 110.
  6. Haerang Choi et al. 2020. Reducing DRAM refresh power consumption by runtime profiling of retention time and dual-row activation. MICPRO 72 (2020).
  7. Jia Deng et al. 2009. Imagenet: A large-scale hierarchical image database. In 2009 IEEE conference on computer vision and pattern recognition. Ieee, 248–255.
  8. Pietro Frigo et al. 2020. TRRespass: Exploiting the many sides of target row refresh. In SP. IEEE, 747–762.
  9. Daniel Gruss et al. 2018. Another flip in the wall of rowhammer defenses. In SP. IEEE, 245–261.
  10. Hasan Hassan et al. 2021. Uncovering in-dram rowhammer protection mechanisms: A new methodology, custom rowhammer patterns, and implications. In MICRO. 1198–1213.
  11. Delving deep into rectifiers: Surpassing human-level performance on imagenet classification. In ICCV. 1026–1034.
  12. Sanghyun Hong et al. 2019. Terminal Brain Damage: Exposing the Graceless Degradation in Deep Neural Networks Under Hardware Fault Attacks.. In USENIX. 497–514.
  13. Patrick Jattke et al. 2022. Blacksmith: Scalable rowhammering in the frequency domain. In SP. IEEE, 716–734.
  14. Marcin Kaczmarski. 2014. Thoughts on intel xeon e5-2600 v2 product family performance optimisation–component selection guidelines.
  15. Dae-Hyun Kim et al. 2014a. Architectural support for mitigating row hammering in DRAM memories. IEEE CAL 14, 1 (2014), 9–12.
  16. Jeremie S Kim et al. 2020. Revisiting rowhammer: An experimental analysis of modern dram devices and mitigation techniques. In ISCA. IEEE, 638–651.
  17. Michael Jaemin Kim et al. 2022. Mithril: Cooperative row hammer protection on commodity dram leveraging managed refresh. In HPCA. IEEE, 1156–1169.
  18. Yoongu Kim et al. 2014b. Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. ACM SIGARCH Computer Architecture News 42, 3 (2014), 361–372.
  19. The CIFAR-10 dataset. online: http://www. cs. toronto. edu/kriz/cifar. html 55 (2014).
  20. Eojin Lee et al. 2019. TWiCe: Preventing row-hammering by exploiting time window counters. In ISCA. 385–396.
  21. Moritz Lipp et al. 2020. Nethammer: Inducing rowhammer faults through network requests. In EuroS&PW. IEEE, 710–719.
  22. Michele Marazzi et al. 2022. Protrr: Principled yet optimal in-dram target row refresh. In SP. IEEE, 735–753.
  23. Michele Marazzi et al. 2023. REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations. In SP. IEEE.
  24. Onur Mutlu and Jeremie S Kim. 2019. Rowhammer: A retrospective. IEEE TCAD 39 (2019).
  25. Ataberk Olgun et al. 2023. DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips. TCAD (2023).
  26. Yeonhong Park et al. 2020. Graphene: Strong yet lightweight row hammer protection. In MICRO. IEEE, 1–13.
  27. Moinuddin Qureshi et al. 2022. Hydra: enabling low-overhead mitigation of row-hammer at ultra-low thresholds via hybrid tracking. In ISCA.
  28. Adnan Siraj Rakin et al. 2019. Bit-flip attack: Crushing neural network with progressive bit search. In ICCV. 1211–1220.
  29. Mark Seaborn and Thomas Dullien. 2015. Exploiting the DRAM rowhammer bug to gain kernel privileges. Black Hat 15 (2015), 71.
  30. Seyed Mohammad Seyedzadeh et al. 2016. Counter-based tree structure for row hammering mitigation in DRAM. CAL 16 (2016).
  31. Seyed Mohammad Seyedzadeh et al. 2018. Mitigating wordline crosstalk using adaptive trees of counters. In ISCA. IEEE, 612–623.
  32. Mungyu Son et al. 2017. Making DRAM stronger against row hammering. In DAC. 1–6.
  33. Jeonghyun Woo et al. 2022. Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems. preprint arXiv:2212.12613 (2022).
  34. Fan Yao et al. 2020. Deephammer: Depleting the intelligence of deep neural networks through targeted chain of bit flips. In USENIX.
  35. Ranyang Zhou et al. 2022a. LT-PIM: An LUT-Based Processing-in-DRAM Architecture With RowHammer Self-Tracking. IEEE Computer Architecture Letters 21, 2 (2022), 141–144.
  36. Ranyang Zhou et al. 2022b. ReD-LUT: Reconfigurable in-DRAM LUTs enabling massive parallel computation. In Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design. 1–8.
  37. Ranyang Zhou et al. 2023a. DNN-Defender: An in-DRAM Deep Neural Network Defense Mechanism for Adversarial Weight Attack. arXiv preprint arXiv:2305.08034 (2023).
  38. Ranyang Zhou et al. 2023b. DRAM-Locker: A General-Purpose DRAM Protection Mechanism against Adversarial DNN Weight Attacks. arXiv preprint arXiv:2312.09027 (2023).
  39. Ranyang Zhou et al. 2023c. P-pim: A parallel processing-in-dram framework enabling row hammer protection. In DATE. IEEE, 1–6.

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