Demonstration of logical qubits and repeated error correction with better-than-physical error rates (2404.02280v3)

Abstract: The promise of quantum computers hinges on the ability to scale to large system sizes, e.g., to run quantum computations consisting of more than 100 million operations fault-tolerantly. This in turn requires suppressing errors to levels inversely proportional to the size of the computation. As a step towards this ambitious goal, we present experiments on a trapped-ion QCCD processor where, through the use of fault-tolerant encoding and error correction, we are able to suppress logical error rates to levels below the physical error rates. In particular, we entangled logical qubits encoded in the [[7,1,3]] code with error rates 9.8 times to 500 times lower than at the physical level, and entangled logical qubits encoded in a [[12,2,4]] code based on Knill's C4/C6 scheme with error rates 4.7 times to 800 times lower than at the physical level, depending on the judicious use of post-selection. Moreover, we demonstrate repeated error correction with the [[12,2,4]] code, with logical error rates below physical circuit baselines corresponding to repeated CNOTs, and show evidence that the error rate per error correction cycle, which consists of over 100 physical CNOTs, approaches the error rate of two physical CNOTs. These results signify a transition from noisy intermediate scale quantum computing to reliable quantum computing, and demonstrate advanced capabilities toward large-scale fault-tolerant quantum computing.

• The paper demonstrates logical qubits with error rates up to 800 times lower than physical qubits using the [[7,1,3]] Steane and [[12,2,4]] Carbon codes.
• It employs high-fidelity Bell state preparation with flagged syndrome extraction to ensure fault-tolerant quantum protocol validation.
• The experiments showcase repeated error correction cycles that maintain performance comparable to physical two-gate sequences, advancing scalable quantum computing.

Evaluation of Logical Qubits and Error Correction Capabilities in Trapped-Ion Processors

This paper presents a detailed examination of quantum error correction (QEC) strategies implemented using a trapped-ion quantum charge-coupled device (QCCD) processor. The research focuses on demonstrating logical qubits with error rates better than those at the physical level, utilizing the $[[7,1,3]]$ Steane code and the $[[12,2,4]]$ Carbon code. The experiments successfully showcase error rates up to 800 times lower than physical error rates in certain configurations, highlighting a promising pathway towards stable, fault-tolerant quantum computing.

Main Contributions

1. Improvement Using Error-Correcting Codes:
   • The research uses two well-known quantum error-correcting codes: the $[[7,1,3]]$ Steane code and the $[[12,2,4]]$ Carbon code. These codes allow logical qubits to have error rates significantly lower than physical qubits.
   • For the Steane code, logical qubits demonstrated error rates between 9.8 to 500 times lower than their unencoded counterparts across different logical operations.
   • The Carbon code achieved logical error rates 4.7 to 800 times lower than physical implementations, depending on the operations and levels of error correction applied.
2. High-Fidelity Bell State Preparation:
   • The research successfully prepares logical Bell states using both the Steane code and Carbon code, showing reductions in error rates through comprehensive correction strategies.
   • Error detection and correction via flagged syndrome extraction were incorporated into these preparations, highlighting the practical implementation of fault-tolerant quantum protocols.
3. Repeated Error Correction:
   • Demonstrations showed repeated quantum error correction cycles using the $[[12,2,4]]$ Carbon code, marking an essential step towards scalable quantum computing systems.
   • Logical circuits were shown to accumulate errors at rates comparable to those of physical two-gate sequences, aligning with theoretical expectations under scalable fault-tolerant computation.

Methodology and Results

The methodology integrated calibration of pre-selection and post-selection strategies based on syndrome measurements. These optimized the error suppression mechanisms, thus improving the post-correlation logical qubit parameters. Further, the research utilized innovative compiler customizations, such as dynamical decoupling and refined scheduling, to mitigate idle errors and transport-related decoherence in the QCCD processor.

For the Bell state preparations:

• The Steane code achieved high accuracy in parity measurements, where logical corrections further refined the results to outperform related unencoded setups.
• The Carbon code utilized pre-and-post selection methodologies that enhanced error rating calculations, leading to superior fidelity in resulting quantum states post-error correction.

The repeated error correction experiments:

• Showed the feasibility of extended correction routines, maintaining logical error rates below the physical circuit baselines.
• Provided evidence of logical circuits surpassing the performance of sequences of comparable physical operations, which is crucial for the next steps in realizing extensive quantum algorithm applications.

Implications and Future Directions

This research underscores significant achievements in suppressing logical error rates below those of physical qubits, heralding advances in the realization of reliable quantum processors. The results indicate a transition point towards scalable quantum computing, where error rates might soon enable practical deployment of quantum algorithms beyond experimental conditions.

The paper's implications are vast, not only in terms of demonstrating a transitionary phase from experimental to practical quantum computing but also in showcasing the layered approach essential for constructing large-scale, fault-resilient quantum systems.

Future directions might consider expanding the depth of logical operations tested, improving the integration of other error-correction codes with potentially lower error thresholds, and exploring more intricate logical gate constructions. Furthermore, continued hardware optimization, as demonstrated in scheduling and coherence management, remains crucial for further refining these outcomes in integrated quantum computing environments.