Papers
Topics
Authors
Recent
Gemini 2.5 Flash
Gemini 2.5 Flash
139 tokens/sec
GPT-4o
7 tokens/sec
Gemini 2.5 Pro Pro
46 tokens/sec
o3 Pro
4 tokens/sec
GPT-4.1 Pro
38 tokens/sec
DeepSeek R1 via Azure Pro
28 tokens/sec
2000 character limit reached

THEMIS: Time, Heterogeneity, and Energy Minded Scheduling for Fair Multi-Tenant Use in FPGAs (2404.00507v3)

Published 31 Mar 2024 in cs.OS and cs.DC

Abstract: Using correct design metrics and understanding the limitations of the underlying technology is critical to developing effective scheduling algorithms. Unfortunately, existing scheduling techniques used \emph{incorrect} metrics and had \emph{unrealistic} assumptions for fair scheduling of multi-tenant FPGAs where each tenant is aimed to share approximately the same number of resources both spatially and temporally. This paper introduces an enhanced fair scheduling algorithm for multi-tenant FPGA use, addressing previous metric and assumption issues, with three specific improvements claimed First, our method ensures spatiotemporal fairness by considering both spatial and temporal aspects, addressing the limitation of prior work that assumed uniform task latency. Second, we incorporate energy considerations into fairness by adjusting scheduling intervals and accounting for energy overhead, thereby balancing energy efficiency with fairness. Third, we acknowledge overlooked aspects of FPGA multi-tenancy, including heterogeneous regions and the constraints on dynamically merging/splitting partially reconfigurable regions. We develop and evaluate our improved fair scheduling algorithm with these three enhancements. Inspired by the Greek goddess of law and personification of justice, we name our fair scheduling solution THEMIS: \underline{T}ime, \underline{H}eterogeneity, and \underline{E}nergy \underline{Mi}nded \underline{S}cheduling. We used the Xilinx Zedboard XC7Z020 to quantify our approach's savings. Compared to previous algorithms, our improved scheduling algorithm enhances fairness between 24.2--98.4\% and allows a trade-off between 55.3$\times$ in energy vs. 69.3$\times$ in fairness. The paper thus informs cloud providers about future scheduling optimizations for fairness with related challenges and opportunities.

Definition Search Book Streamline Icon: https://streamlinehq.com
References (33)
  1. A. Khawaja, J. Landgraf, R. Prakash, M. Wei, E. Schkufza, and C. J. Rossbach, “Sharing, Protection, and Compatibility for Reconfigurable Fabric with AMORPHOS,” in 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 18), 2018, pp. 107–127.
  2. D. Korolija, T. Roscoe, and G. Alonso, “Do OS abstractions make sense on FPGAs?” in 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20), 2020, pp. 991–1010.
  3. S. A. Fahmy, K. Vipin, and S. Shreejith, “Virtualized FPGA Accelerators for Efficient Cloud Computing,” in 2015 IEEE 7th International Conference on Cloud Computing Technology and Science (CloudCom).   IEEE, 2015, pp. 430–435.
  4. Y. Zha and J. Li, “Virtualizing FPGAs in the Cloud,” in ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2020, pp. 845–858.
  5. J. Ma, G. Zuo, K. Loughlin, X. Cheng, Y. Liu, A. M. Eneyew, Z. Qi, and B. Kasikci, “A Hypervisor for Shared-Memory FPGA Platforms,” in Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, 2020, pp. 827–844.
  6. A. Vaishnav, K. D. Pham, D. Koch, and J. Garside, “Resource Elastic Virtualization for FPGAs using OpenCL,” in IEEE International Conference on Field Programmable Logic and Applications (FPL), 2018, pp. 111–1117.
  7. J. Mohan, A. Phanishayee, J. Kulkarni, and V. Chidambaram, “Looking beyond GPUs for DNN Scheduling on Multi-Tenant Clusters,” in 16th USENIX Symposium on Operating Systems Design and Implementation (OSDI 22), 2022, pp. 579–596.
  8. F. Yu, D. Wang, L. Shangguan, M. Zhang, C. Liu, and X. Chen, “A Survey of Multi-tenant Deep Learning Inference on GPU,” arXiv preprint arXiv:2203.09040, 2022.
  9. D. Shue, M. J. Freedman, and A. Shaikh, “Performance Isolation and Fairness for Multi-tenant Cloud Storage,” in presented as part of the 10th USENIX Symposium on Operating Systems Design and Implementation (OSDI 12), 2012, pp. 349–362.
  10. V. Narasayya, S. Das, M. Syamala, B. Chandramouli, and S. Chaudhuri, “SQLVM: Performance Isolation in Multi-Tenant Relational Database-as-a-Service,” in CIDR 2013, 2013.
  11. A. Duhamel and S. Pillement, “QoS Aware Design-Time/Run-Time Manager for FPGA-Based Embedded Systems,” in Design and Architecture for Signal and Image Processing: 15th International Workshop, DASIP 2022, Budapest, Hungary, June 20–22, 2022, Proceedings.   Springer, 2022, pp. 96–107.
  12. C. Kao, “Benefits of Partial Reconfiguration,” Xcell journal, vol. 55, pp. 65–67, 2005.
  13. A. Mehrabi, D. J. Sorin, and B. C. Lee, “Spatiotemporal Strategies for Long-Term FPGA Resource Management,” in 2022 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).   IEEE, 2022, pp. 198–209.
  14. M. Huang, D. Wu, C. H. Yu, Z. Fang, M. Interlandi, T. Condie, and J. Cong, “Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale,” in Proceedings of the Seventh ACM Symposium on Cloud Computing, 2016, pp. 456–469.
  15. O. Knodel and R. G. Spallek, “RC3E: Provision and Management of Reconfigurable Hardware Accelerators in a Cloud Environment v,” arXiv preprint arXiv:1508.06843, 2015.
  16. E. Karabulut, C. Yuvarajappa, M. I. Shaik, S. Potluri, A. Awad, and A. Aysu, “PR Crisis: Analyzing and Fixing Partial Reconfiguration in Multi-Tenant Cloud FPGAs,” in ACM Workshop on Attacks and Solutions in Hardware Security (ASHES), 2022, pp. 101–106.
  17. M. A. Rihani et al, “Dynamic and Partial Reconfiguration Power Consumption Runtime Measurements Analysis for ZYNQ SoC Devices ,” in IEEE International Symposium on Wireless Communication Systems, 2016, pp. 592–596.
  18. N. Kulkarni, G. Gonzalez-Pumariega, A. Khurana, C. A. Shoemaker, C. Delimitrou, and D. H. Albonesi, “Cuttlesys: Data-driven resource management for interactive services on Reconfigurable Multicores,” in 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).   IEEE, 2020, pp. 650–664.
  19. S. M. Zahedi and B. C. Lee, “REF: Resource Elasticity Fairness with Sharing Incentives for Multiprocessors,” ACM Sigplan Notices, vol. 49, no. 4, pp. 145–160, 2014.
  20. A. Ghodsi, M. Zaharia, B. Hindman, A. Konwinski, S. Shenker, and I. Stoica, “Dominant Resource Fairness: Fair Allocation of Multiple Resource Types,” in 8th USENIX symposium on networked systems design and implementation (NSDI 11), 2011.
  21. D. C. Parkes, A. D. Procaccia, and N. Shah, “Beyond Dominant Resource Fairness: Extensions, Limitations, and Indivisibilities,” ACM Transactions on Economics and Computation (TEAC), vol. 3, no. 1, pp. 1–22, 2015.
  22. E. L. Hahne, “Round-Robin Scheduling for Max-Min Fairness in Data Network,” IEEE Journal on Selected Areas in communications, vol. 9, no. 7, pp. 1024–1039, 1991.
  23. J. L. Falk, “Schedule-Induced Polydipsia as a Function of Fixed Interval Length,” Journal of the experimental analysis of Behavior, vol. 9, no. 1, pp. 37–39, 1966.
  24. B. Reagen, R. Adolf, Y. S. Shao, G.-Y. Wei, and D. Brooks, “MachSuite: Benchmarks for Accelerator Design and Customized Architectures,” in 2014 IEEE International Symposium on Workload Characterization (IISWC).   IEEE, 2014, pp. 110–119.
  25. K. Vipin and S. A. Fahmy, “ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq,” IEEE Embedded Systems Letters, vol. 6, no. 3, pp. 41–44, 2014.
  26. K. Jozwik, H. Tomiyama, S. Honda, and H. Takada, “A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems,” in 2010 International Conference on Field Programmable Logic and Applications.   IEEE, 2010, pp. 352–355.
  27. B. Sultana, A. Ullah, A. A. Malik, A. Zahir, P. Reviriego, F. B. Muslim, N. Ullah, and W. Ahmad, “VR-ZYCAP: A Versatile Resource-Level ICAP Controller for ZYNQ SOC,” Electronics, vol. 10, no. 8, p. 899, 2021.
  28. M. Liu, W. Kuehn, Z. Lu, and A. Jantsch, “Run-time Partial Reconfiguration Speed Investigation and Architectural Design Space Exploration,” in 2009 International Conference on Field Programmable Logic and Applications.   IEEE, 2009, pp. 498–502.
  29. E. J. McDonald, “Runtime FPGA Partial Reconfiguration,” in 2008 IEEE Aerospace Conference.   IEEE, 2008, pp. 1–7.
  30. K. Vipin and S. A. Fahmy, “A High Speed Open Source Controller for FPGA Partial Reconfiguration,” in 2012 International Conference on Field-Programmable Technology.   IEEE, 2012, pp. 61–66.
  31. F. Duhem, F. Muller, and P. Lorenzini, “FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA,” in Reconfigurable Computing: Architectures, Tools and Applications: 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings 7.   Springer, 2011, pp. 253–260.
  32. S. Liu, R. N. Pittman, A. Forin, and J.-L. Gaudiot, “Achieving Energy Efficiency through Runtime Partial Reconfiguration on Reconfigurable Systems,” ACM Transactions on Embedded Computing Systems (TECS), vol. 12, no. 3, pp. 1–21, 2013.
  33. A. R. Bucknall and S. A. Fahmy, “ZyPR: End-to-End Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge,” ACM Transactions on Reconfigurable Technology and Systems, 2023.

Summary

We haven't generated a summary for this paper yet.

X Twitter Logo Streamline Icon: https://streamlinehq.com