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DECOR: Enhancing Logic Locking Against Machine Learning-Based Attacks (2403.01789v1)

Published 4 Mar 2024 in cs.CR, cs.SY, and eess.SY

Abstract: Logic locking (LL) has gained attention as a promising intellectual property protection measure for integrated circuits. However, recent attacks, facilitated by ML, have shown the potential to predict the correct key in multiple LL schemes by exploiting the correlation of the correct key value with the circuit structure. This paper presents a generic LL enhancement method based on a randomized algorithm that can significantly decrease the correlation between locked circuit netlist and correct key values in an LL scheme. Numerical results show that the proposed method can efficiently degrade the accuracy of state-of-the-art ML-based attacks down to around 50%, resulting in negligible advantage versus random guessing.

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References (33)
  1. B. Tan, R. Karri, N. Limaye, A. Sengupta, O. Sinanoglu, M. M. Rahman, S. Bhunia, D. Duvalsaint, A. Rezaei, Y. Shen, et al., “Benchmarking at the frontier of hardware security: Lessons from logic locking,” arXiv preprint arXiv:2006.06806, 2020.
  2. R. S. Rajarathnam, Y. Lin, Y. Jin, and D. Z. Pan, “ReGDS: A reverse engineering framework from GDSII to gate-level netlist,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 154–163, 2020.
  3. T. Meade, S. Zhang, and Y. Jin, “Netlist reverse engineering for high-level functionality reconstruction,” in 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 655–660, IEEE, 2016.
  4. J. Geist, T. Meade, S. Zhang, and Y. Jin, “RELIC-FUN: Logic identification through functional signal comparisons,” in Proc. Design Automation Conf. (DAC), pp. 1–6, 2020.
  5. S. Dutta Chowdhury, K. Yang, and P. Nuzzo, “ReIGNN: State register identification using graph neural networks for circuit reverse engineering,” in Proceedings of the 40th International Conference on Computer-Aided Design, pp. 1–9, 2021.
  6. Y. Zhang, Y. Hu, P. Nuzzo, and P. A. Beerel, “TriLock: IC protection with tunable corruptibility and resilience to SAT and removal attacks,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1329–1334, IEEE, 2022.
  7. J. A. Roy, F. Koushanfar, and I. L. Markov, “Ending piracy of integrated circuits,” Computer, vol. 43, no. 10, pp. 30–38, 2010.
  8. J. Rajendran, H. Zhang, C. Zhang, G. S. Rose, Y. Pino, O. Sinanoglu, and R. Karri, “Fault analysis-based logic encryption,” IEEE Trans. Computers, vol. 64, no. 2, pp. 410–424, 2013.
  9. M. Yasin, J. J. Rajendran, O. Sinanoglu, and R. Karri, “On improving the security of logic locking,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 9, pp. 1411–1424, 2016.
  10. M. Yasin, B. Mazumdar, J. J. Rajendran, and O. Sinanoglu, “SARLock: SAT attack resistant logic locking,” in IEEE Int. Symp. Hardware Oriented Security and Trust (HOST), pp. 236–241, 2016.
  11. Y. Hu, K. Yang, S. Nazarian, and P. Nuzzo, “SANSCrypt: A sporadic-authentication-based sequential logic encryption scheme,” in IFIP/IEEE Int. Conf. Very Large Scale Integration (VLSI-SoC), pp. 129–134, 2020.
  12. S. D. Chowdhury, G. Zhang, Y. Hu, and P. Nuzzo, “Enhancing SAT-attack resiliency and cost-effectiveness of reconfigurable-logic-based circuit obfuscation,” in Int. Symp. Circuits and Systems (ISCAS), pp. 1–5, IEEE, 2021.
  13. P. Chakraborty, J. Cruz, and S. Bhunia, “SAIL: Machine learning guided structural analysis attack on hardware obfuscation,” in Asian Hardware Oriented Security and Trust Symp. (AsianHOST), pp. 56–61, IEEE, 2018.
  14. Y. Hu, K. Yang, S. Dutta Chowdhury, and P. Nuzzo, “Risk-aware cost-effective design methodology for integrated circuit locking,” in Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 1182–1185, IEEE, 2021.
  15. D. Sisejkovic, L. M. Reimann, E. Moussavi, F. Merchant, and R. Leupers, “Logic locking at the frontiers of machine learning: A survey on developments and opportunities,” in 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), pp. 1–6, IEEE, 2021.
  16. D. Sisejkovic, F. Merchant, L. M. Reimann, H. Srivastava, A. Hallawa, and R. Leupers, “Challenging the security of logic locking schemes in the era of deep learning: A neuroevolutionary approach,” arXiv preprint arXiv:2011.10389, 2020.
  17. A. Raj, N. Avula, P. Das, D. Sisejkovic, F. Merchant, and A. Acharyya, “DeepAttack: A deep learning based oracle-less attack on logic locking,” in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5, 2023.
  18. L. Alrahis, S. Patnaik, M. Shafique, and O. Sinanoglu, “OMLA: An oracle-less machine learning-based attack on logic locking,” Transactions on Circuits and Systems II: Express Briefs, 2021.
  19. L. Alrahis, S. Patnaik, J. Knechtel, H. Saleh, B. Mohammad, M. Al-Qutayri, and O. Sinanoglu, “UNSAIL: Thwarting oracle-less machine learning attacks on logic locking,” Transactions on Information Forensics and Security, vol. 16, pp. 2508–2523, 2021.
  20. D. Sisejkovic, F. Merchant, L. M. Reimann, and R. Leupers, “Deceptive logic locking for hardware integrity protection against machine learning attacks,” Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021.
  21. S. D. Chowdhury, K. Yang, and P. Nuzzo, “SimLL: Similarity-based logic locking against machine learning attacks,” in 60th ACM/IEEE Design Automation Conference (DAC), pp. 1–6, IEEE, 2023.
  22. N. Limaye, E. Kalligeros, N. Karousos, I. G. Karybali, and O. Sinanoglu, “Thwarting all logic locking attacks: Dishonest oracle with truly random logic locking,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 9, pp. 1740–1753, 2020.
  23. Y. Xie and A. Srivastava, “Anti-SAT: Mitigating SAT attack on logic locking,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 2, pp. 199–207, 2018.
  24. P. Subramanyan, S. Ray, and S. Malik, “Evaluating the security of logic encryption algorithms,” in IEEE Int. Symp. Hardware Oriented Security and Trust (HOST), pp. 137–143, 2015.
  25. L. Alrahis, S. Patnaik, F. Khalid, M. A. Hanif, H. Saleh, M. Shafique, and O. Sinanoglu, “GNNUnlock: Graph neural networks-based oracle-less unlocking scheme for provably secure logic locking,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 780–785, IEEE, 2021.
  26. M. Yasin, A. Sengupta, M. T. Nabeel, M. Ashraf, J. J. Rajendran, and O. Sinanoglu, “Provably-secure logic locking: From theory to practice,” in Proc. SIGSAC Conf. Computer and Communications Security, pp. 1601–1618, 2017.
  27. H. Zhou, “A humble theory and application for logic encryption,” IACR Cryptology ePrint Archive, vol. 2017, p. 696, 2017.
  28. Y. Hu, V. V. Menon, A. Schmidt, J. Monson, M. French, and P. Nuzzo, “Security-driven metrics and models for efficient evaluation of logic encryption schemes,” in ACM-IEEE MEMOCODE, pp. 1–5, 2019.
  29. M. C. Hansen, H. Yalcin, and J. P. Hayes, “Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering,” IEEE Design & Test of Computers, vol. 16, no. 3, pp. 72–80, 1999.
  30. S. Davidson, “ITC’99 benchmark circuits-preliminary results,” in International Test Conference 1999. Proceedings (IEEE Cat. No. 99CH37034), pp. 1125–1125, 1999.
  31. Silvaco, “45nm open cell library.” Available at https://si2.org/open-cell-library/.
  32. L. Li and A. Orailoglu, “Redundancy attack: Breaking logic locking through oracleless rationality analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 4, pp. 1044–1057, 2022.
  33. Y. Hu, Y. Zhang, K. Yang, D. Chen, P. A. Beerel, and P. Nuzzo, “On the security of sequential logic locking against oracle-guided attacks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 11, pp. 3628–3641, 2023.

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