Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis (2402.18736v2)

Abstract: Processing-using-DRAM (PuD) is an emerging paradigm that leverages the analog operational properties of DRAM circuitry to enable massively parallel in-DRAM computation. PuD has the potential to reduce or eliminate costly data movement between processing elements and main memory. Prior works experimentally demonstrate three-input MAJ (MAJ3) and two-input AND and OR operations in commercial off-the-shelf (COTS) DRAM chips. Yet, demonstrations on COTS DRAM chips do not provide a functionally complete set of operations. We experimentally demonstrate that COTS DRAM chips are capable of performing 1) functionally-complete Boolean operations: NOT, NAND, and NOR and 2) many-input (i.e., more than two-input) AND and OR operations. We present an extensive characterization of new bulk bitwise operations in 256 off-the-shelf modern DDR4 DRAM chips. We evaluate the reliability of these operations using a metric called success rate: the fraction of correctly performed bitwise operations. Among our 19 new observations, we highlight four major results. First, we can perform the NOT operation on COTS DRAM chips with a 98.37% success rate on average. Second, we can perform up to 16-input NAND, NOR, AND, and OR operations on COTS DRAM chips with high reliability (e.g., 16-input NAND, NOR, AND, and OR with an average success rate of 94.94%, 95.87%, 94.94%, and 95.85%, respectively). Third, data pattern only slightly affects bitwise operations. Our results show that executing NAND, NOR, AND, and OR operations with random data patterns decreases the success rate compared to all logic-1/logic-0 patterns by 1.39%, 1.97%, 1.43%, and 1.98%, respectively. Fourth, bitwise operations are highly resilient to temperature changes, with small success rate fluctuations of at most 1.66% when the temperature is increased from 50C to 95C. We open-source our infrastructure at https://github.com/CMU-SAFARI/FCDRAM

• The paper demonstrates that unmodified DDR4 DRAM chips can perform functionally complete Boolean operations with success rates up to 98.37%.
• It employs an FPGA-based testing infrastructure to evaluate operations like NOT, NAND, NOR, AND, and OR, showing resilience to data pattern and temperature variations.
• The results indicate that integrating computation into DRAM can reduce data transfer overhead and power consumption, paving the way for future in-memory processing architectures.

Functionally Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis

The paper "Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis" explores the capabilities of processing using DRAM (PuD), specifically focusing on unmodified commercial off-the-shelf (COTS) DRAM chips. It explores their ability to perform functionally complete Boolean operations, a significant leap in using memory not just for storage but also for computation.

Key Findings and Methodology

The authors focus on harnessing the analog operational properties of DRAM circuitry to perform computations in-memory, reducing the necessity of transferring data between processing elements and memory. The paper primarily investigates the execution of NOT, NAND, and NOR operations, and demonstrates many-input (up to 16-input) AND and OR operations directly in DRAM chips. These operations are possible through a mechanism called simultaneous multiple-row activation in neighboring subarrays, which enables the chips to execute logic functions at a high success rate.

The experimental analysis was performed using 256 modern DDR4 DRAM chips, evaluating the reliability of these operations with success rates as a key metric. The success rate metrics were impressive: NOT operations achieved an average success rate of 98.37%, while NAND, NOR, AND, and OR operations with 16 inputs exhibited success rates of 94.94%, 95.87%, 94.94%, and 95.85% respectively.

Experimental Setup and Methodology

The methodology involved extensive testing using an FPGA-based DRAM testing infrastructure known as DRAM Bender. This allowed the researchers to precisely control DRAM commands and evaluate the performance across different DRAM architectures and conditions such as temperature changes and varying data patterns.

Importantly, the paper found that data patterns slightly affected success rates, demonstrating resilience to variations, which is crucial for practical uses. Temperature sensitivity was also low, with only a maximum of 1.66% success rate fluctuation over a temperature span from 50°C to 95°C.

Implications and Future Directions

The implications of these findings are profound. They suggest that using DRAM as a computation substrate can enable lower power consumption and increased performance by reducing data movement between the processor and memory. This approach aligns with the ongoing trend toward building more efficient computing systems that integrate computational functions more deeply with memory systems, notably succinct with the advent of in-memory processing paradigms.

The potential of functionally complete operations opens pathways for future DRAM designs to explicitly embrace computational capabilities. However, current constraints, such as limited inputs and different behavior among DRAM manufacturers (e.g., Samsung and Micron showing limited capability), highlight the need for further research. Additionally, this paper provides a groundwork that may encourage future work on DRAM chips by showcasing the potential for even greater computational roles, possibly leading to standardized support for processing tasks within DRAM modules.

Conclusion

This paper highlights a key transition in how DRAM is perceived in relation to computational capacity. Traditionally seen as a passive data storage element, DRAM chips' ability to perform Boolean logic operations in-memory underlines a potential paradigm shift toward processing-in-memory architectures, advocating for enhanced data processing techniques that are both energy-efficient and performance-oriented. Future research and development are encouraged to further extend these capabilities and address current technological limitations.