Multiple-Error-Correcting Codes for Analog Computing on Resistive Crossbars (2402.13503v1)
Abstract: Error-correcting codes over the real field are studied which can locate outlying computational errors when performing approximate computing of real vector--matrix multiplication on resistive crossbars. Prior work has concentrated on locating a single outlying error and, in this work, several classes of codes are presented which can handle multiple errors. It is first shown that one of the known constructions, which is based on spherical codes, can in fact handle multiple outlying errors. A second family of codes is then presented with $\zeroone$~parity-check matrices which are sparse and disjunct; such matrices have been used in other applications as well, especially in combinatorial group testing. In addition, a certain class of the codes that are obtained through this construction is shown to be efficiently decodable. As part of the study of sparse disjunct matrices, this work also contains improved lower and upper bounds on the maximum Hamming weight of the rows in such matrices.
- B. E. Boser, E. Sackinger, J. Bromley, Y. L. Cun, and L. D. Jackel, “An analog neural network processor with programmable topology,” IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 2017–2025, Dec. 1991.
- J. Bourgain, S. J. Dilworth, K. Ford, S. Konyagin, and D. Kutzarova, “Explicit constructions of RIP matrices and related problems,” Duke Math. J., vol. 159, no. 1, pp. 145–185, 2011.
- E. Candès, “The restricted isometry property and its implications for compressed sensing,” C.R. Acad. Sci. Paris, Ser. I, vol. 346, pp. 589–592, 2008.
- E. Candès, J. Romberg, and T. Tao, “Robust uncertainty principles: Exact signal reconstruction from highly incomplete frequency information,” IEEE Trans. Inf. Theory, vol. 52, no. 2, pp. 489–509, Feb. 2006.
- D. Donoho, “Compressed sensing,” IEEE Trans. Inf. Theory, vol. 52, no. 4, pp. 1289–1306, Apr. 2006.
- A. G. D’yachkov and V. V. Rykov, “Bounds on the length of disjunctive codes,” Probl. Peredachi Inf., vol. 18, no. 3, pp. 7–13, 1982.
- Z. Füredi, “On r𝑟ritalic_r-cover-free families,” J. Combin. Theory Ser. A, vol. 73, no. 1, pp. 172–173, 1996.
- M. Hu, C. E. Graves, C. Li, Y. Li, N. Ge, E. Montgomery, N. Davila, H. Jiang, R. S. Williams, J. J. Yang, Q. Xia, and J. P. Strachan, “Memristor-based analog computation and neural network classification with a dot product engine,” in Adv. Mater., vol. 30, Mar. 2018, paper no. 1705914.
- M. Hu, J. P. Strachan, Z. Li, E. M. Grafals, N. Davila, C. Graves, S. Lam, N. Ge, J. Yang, and R. S. Williams, “Dot-product engine for neuromorphic computing: Programming 1T1M crossbar to accelerate matrix-vector multiplication,” in Proc. 53rd ACM/EDAC/IEEE Design Automat. Conf. (DAC), Austin, TX, 2016, paper no. 19.
- H. A. Inan, P. Kairouz, and A. Özgür, “Sparse combinatorial group testing,” IEEE Trans. Inf. Theory, vol. 66, no. 5, pp. 2729–2742, May 2020.
- G. Katona and A. Seress, “Greedy construction of nearly regular graphs,” European J. of Combin., vol. 14, pp. 213–229, 1993.
- W. Kautz and R. Singleton, “Nonrandom binary superimposed codes,” IEEE Trans. Inf. Theory, vol. 10, no. 4, pp. 363–377, Oct. 1964.
- F. J. Kub, K. K. Moon, I. A. Mack, and F. M. Long, “Programmable analog vector-matrix multipliers,” IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 207–214, Feb. 1990.
- D. Lubell, “A short proof of Sperner’s lemma,” J. Combin. Theory Ser. A, vol. 1, no. 2, p. 299, 1966.
- E. Porat and A. Rothschild, “Explicit non-adaptive combinatorial group testing schemes,” IEEE Trans. Inf. Theory, vol. 57, no. 12, pp. 7982–7989, Dec. 2011.
- R. M. Roth, “Fault-tolerant dot-product engines,” IEEE Trans. Inf. Theory, vol. 65, no. 4, pp. 2046–2057, Apr. 2019.
- ——, “Analog error-correcting codes,” IEEE Trans. Inf. Theory, vol. 66, no. 7, pp. 4075–4088, Jul. 2020.
- ——, “Fault-tolerant neuromorphic computing on nanoscale crossbar architectures,” in Proc. 2020 IEEE Inf. Theory Workshop (ITW), Mumbai, India, 2022, pp. 202–207.
- ——, “Correction to “analog error-correcting codes”,” IEEE Trans. Inf. Theory, vol. 69, no. 6, pp. 3793–3794, Jan. 2023.
- A. Shafiee, A. Nag, N. Muralimanohar, R. Balasubramonian, J. P. Strachan, M. Hu, R. S. Williams, and V. Srikumar, “ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars,” in Proc. ACM/IEEE 43rd Annu. Int. Symp. Comput. Archit. (ISCA), Seoul, Korea, Jun. 2016, pp. 14–26.