CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks (2401.07142v1)
Abstract: Logic locking proposed to protect integrated circuits from serious hardware threats has been studied extensively over a decade. In these years, many efficient logic locking techniques have been proven to be broken. The state-of-the-art logic locking techniques, including the prominent corrupt and correct (CAC) technique, are resilient to satisfiability (SAT)-based and removal attacks, but vulnerable to structural analysis attacks. To overcome this drawback, this paper introduces an improved version of CAC, called CAC 2.0, which increases the search space of structural analysis attacks using obfuscation. To do so, CAC 2.0 locks the original circuit twice, one after another, on different nodes with different number of protected primary inputs using CAC, while hiding original protected primary inputs among decoy primary inputs. This paper also introduces an open source logic locking tool, called HIID, equipped with well-known techniques including CAC 2.0. Our experiments show that CAC 2.0 is resilient to existing SAT-based, removal, and structural analysis attacks. To achieve this, it increases the number of key inputs at most 4x and the gate-level area between 30.2% and 0.8% on circuits with low and high complexity with respect to CAC.
- Defence Science Board Task Force. (2015, February) On High Performance Microchip Supply Chain. [Online]. Available: https://dsb.cto.mil/reports/2000s/ADA435563.pdf
- J. A. Roy, F. Koushanfar, and I. L. Markov, “EPIC: Ending Piracy of Integrated Circuits,” in DATE, 2008, pp. 1069–1074.
- S. Dupuis, P. Ba, G. Di Natale, M. Flottes, and B. Rouzeyre, “A Novel Hardware Logic Encryption Technique for Thwarting Illegal Overproduction and Hardware Trojans,” in IOLTS, 2014, pp. 49–54.
- P. Subramanyan, S. Ray, and S. Malik, “Evaluating the Security of Logic Encryption Algorithms,” in HOST, 2015, pp. 137–143.
- M. Yasin, A. Sengupta, M. T. Nabeel, M. Ashraf, J. Rajendran, and O. Sinanoglu, “Provably-Secure Logic Locking: From Theory To Practice,” in ACM CCS, 2017, pp. 1601–1618.
- K. Shamsi, M. Li, T. Meade, Z. Zhao, D. Z. Pan, and Y. Jin, “Cyclic Obfuscation for Creating SAT-Unresolvable Circuits,” in GLVLSI, 2017, p. 173–178.
- M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran, “Removal Attacks on Logic Locking and Camouflaging Techniques,” IEEE TETC, vol. 8, no. 2, pp. 517–532, 2020.
- D. Sirone and P. Subramanyan, “Functional Analysis Attacks on Logic Locking,” in DATE, 2019, pp. 936–939.
- H. Zhou, R. Jiang, and S. Kong, “CycSAT: SAT-based Attack on Cyclic Logic Encryptions,” in ICCAD, 2017, pp. 49–56.
- K. Shamsi, T. Meade, M. Li, D. Z. Pan, and Y. Jin, “On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes,” IEEE TIFS, vol. 14, no. 2, pp. 347–359, 2019.
- Y. Xie and A. Srivastava, “Anti-SAT: Mitigating SAT Attack on Logic Locking,” IEEE TCAD, vol. 38, no. 2, pp. 199–207, 2019.
- M. Yasin, B. Mazumdar, J. Rajendran, and O. Sinanoglu, “SARLock: SAT Attack Resistant Logic Locking,” in HOST, 2016, pp. 236–241.
- M. Yasin, A. Sengupta, B. C. Schafer, Y. Makris, O. Sinanoglu, and J. Rajendran, “What to Lock? Functional and Parametric Locking,” in GLSVLSI, 2017, p. 351–356.
- B. Tan et al., “Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking,” 2020. [Online]. Available: https://arxiv.org/abs/2006.06806
- L. Aksoy, M. Yasin, and S. Pagliarini, “KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking,” in DATE, 2024, accepted for publication.
- B. Shakya, X. Xu, M. Tehranipoor, and D. Forte, “CAS-Lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme,” IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2020, no. 1, pp. 175–202, 2019.
- A. Sengupta, M. Nabeel, N. Limaye, M. Ashraf, and O. Sinanoglu, “Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective,” IEEE TCAD, vol. 39, no. 12, pp. 4439–4452, 2020.
- J. Zhou and X. Zhang, “Generalized SAT-Attack-Resistant Logic Locking,” IEEE TIFS, vol. 16, pp. 2581–2592, 2021.
- Y. Liu, M. Zuzak, Y. Xie, A. Chakraborty, and A. Srivastava, “Strong Anti-SAT: Secure and Effective Logic Locking,” in ISQED, 2020, pp. 199–205.
- H. Zhou, A. Rezaei, and Y. Shen, “Resolving the Trilemma in Logic Encryption,” in ICCAD, 2019, pp. 1–8.
- L. Aksoy, Q.-L. Nguyen, F. Almeida, J. Raik, M.-L. Flottes, S. Dupuis, and S. Pagliarini, “Hybrid Protection of Digital FIR Filters,” IEEE TVLSI, vol. 31, no. 6, pp. 812–825, 2023.
- K. Shamsi and Y. Jin, “In Praise of Exact-Functional-Secrecy in Circuit Locking,” IEEE TIFS, vol. 16, no. 1, pp. 5225–5238, 2021.
- L. Li and A. Orailoglu, “Piercing Logic Locking Keys through Redundancy Identification,” in DATE, 2019, pp. 540–545.
- Y. Zhang, P. Cui, Z. Zhou, and U. Guin, “TGA: An Oracle-Less and Topology-Guided Attack on Logic Locking,” in ASHES, 2019, p. 75–83.
- A. Alaql, M. M. Rahman, and S. Bhunia, “SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking,” IEEE TVLSI, vol. 29, no. 8, pp. 1529–1542, 2021.
- N. Limaye, S. Patnaik, and O. Sinanoglu, “Valkyrie: Vulnerability Assessment Tool and Attack for Provably-Secure Logic Locking Techniques,” IEEE TIFS, vol. 17, pp. 744–759, 2022.
- Y. Shen and H. Zhou, “Double DIP: Re-Evaluating Security of Logic Encryption Algorithms,” in GLSVLSI, 2017, pp. 179–184.
- K. Shamsi, M. Li, T. Meade, Z. Zhao, D. Z. Pan, and Y. Jin, “AppSAT: Approximately Deobfuscating Integrated Circuits,” in HOST, 2017, pp. 95–100.
- Z. Han, M. Yasin, and J. J. Rajendran, “Does Logic Locking Work with EDA Tools?” in USENIX Security Symposium, 2021, pp. 1055–1072.
- S. Patnaik, N. Limaye, and O. Sinanoglu, “Hide and Seek: Seeking the (Un)-Hidden Key in Provably-Secure Logic Locking Techniques,” IEEE TIFS, vol. 17, pp. 3290–3305, 2022.
- A. Mishchenko. ABC: System for Sequential Logic Synthesis and Formal Verification. [Online]. Available: https://github.com/berkeley-abc/abc
- M. Soos. Cryptominisat SAT Solver. [Online]. Available: https://github.com/msoos/cryptominisat
- L. Aksoy. HIID: A Logic Locking Tool. [Online]. Available: https://github.com/leventaksoy/hiid