Papers
Topics
Authors
Recent
Gemini 2.5 Flash
Gemini 2.5 Flash
102 tokens/sec
GPT-4o
59 tokens/sec
Gemini 2.5 Pro Pro
43 tokens/sec
o3 Pro
6 tokens/sec
GPT-4.1 Pro
50 tokens/sec
DeepSeek R1 via Azure Pro
28 tokens/sec
2000 character limit reached

Compiler Testing With Relaxed Memory Models (2310.12337v3)

Published 18 Oct 2023 in cs.PL, cs.AR, and cs.SE

Abstract: Finding bugs is key to the correctness of compilers in wide use today. If the behaviour of a compiled program, as allowed by its architecture memory model, is not a behaviour of the source program under its source model, then there is a bug. This holds for all programs, but we focus on concurrency bugs that occur only with two or more threads of execution. We focus on testing techniques that detect such bugs in C/C++ compilers. We seek a testing technique that automatically covers concurrency bugs up to fixed bounds on program sizes and that scales to find bugs in compiled programs with many lines of code. Otherwise, a testing technique can miss bugs. Unfortunately, the state-of-the-art techniques are yet to satisfy all of these properties. We present the T\'el\'echat compiler testing tool for concurrent programs. T\'el\'echat compiles a concurrent C/C++ program and compares source and compiled program behaviours using source and architecture memory models. We make three claims: T\'el\'echat improves the state-of-the-art at finding bugs in code generation for multi-threaded execution, it is the first public description of a compiler testing tool for concurrency that is deployed in industry, and it is the first tool that takes a significant step towards the desired properties. We provide experimental evidence suggesting T\'el\'echat finds bugs missed by other state-of-the-art techniques, case studies indicating that T\'el\'echat satisfies the properties, and reports of our experience deploying T\'el\'echat in industry regression testing.

Definition Search Book Streamline Icon: https://streamlinehq.com
References (78)
  1. GPU Concurrency: Weak Behaviours and Programming Assumptions. In Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems (New York, NY, USA, 2015), ASPLOS ’15, ACM, p. 577–591.
  2. Syntax and semantics of the weak consistency model specification language cat. CoRR abs/1608.07531 (2016).
  3. Armed Cats: Formal Concurrency Modelling at Arm. ACM Trans. Program. Lang. Syst. 43, 2 (July 2021).
  4. Don’t Sit on the Fence: A Static Analysis Approach to Automatic Fence Insertion. ACM Trans. Program. Lang. Syst. 39, 2 (May 2017).
  5. herdtools7. https://github.com/herd/herdtools7, 2021. Accessed: 2019-10-06.
  6. NEON Architecture Tests. https://github.com/herd/herdtools7/tree/master/herd/tests/instructions/AArch64.neon, 2021. Accessed: 2022-11-29.
  7. SVE Architecture Pull Request. https://github.com/herd/herdtools7/pull/414, 2021.
  8. ARM memory model. https://github.com/herd/herdtools7/blob/master/herd/libdir/arm.cat, 2022.
  9. Frightening Small Children and Disconcerting Grown-ups: Concurrency in the Linux Kernel. In Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems (New York, NY, USA, 2018), ASPLOS ’18, ACM, pp. 405–418.
  10. Litmus: Running Tests Against Hardware. In Proceedings of the 17th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Part of the Joint European Conferences on Theory and Practice of Software (Berlin, Heidelberg, 2011), TACAS’11/ETAPS’11, Springer-Verlag, pp. 41–44.
  11. Fences in Weak Memory Models (Extended Version). Form. Methods Syst. Des. 40, 2 (Apr. 2012), 170–205.
  12. Herding Cats: Modelling, Simulation, Testing, and Data Mining for Weak Memory. ACM Trans. Program. Lang. Syst. 36, 2 (July 2014), 7:1–7:74.
  13. Arm-Limited. Arm Morello Program. https://developer.arm.com/architectures/cpu-architecture/a-profile/morello. Accessed: 2023-03-23.
  14. Arm-Limited. Arm Architecture Reference Manual. Addison-Wesley Longman Publishing Co., Inc., Boston, MA, USA, 2023.
  15. Isla: Integrating full-scale ISA semantics and axiomatic concurrency models. In In Proc. 33rd International Conference on Computer-Aided Verification (July 2021).
  16. On the Verification Problem for Weak Memory Models. In Proceedings of the 37th Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (New York, NY, USA, 2010), POPL ’10, Association for Computing Machinery, p. 7–18.
  17. The Oracle Problem in Software Testing: A Survey. IEEE Trans. Softw. Eng. 41, 5 (May 2015), 507–525.
  18. Overhauling SC Atomics in C11 and OpenCL. In Proceedings of the 43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (New York, NY, USA, 2016), POPL ’16, Association for Computing Machinery, p. 634–648.
  19. Batty, M. J. The C11 and C++11 Concurrency Model. PhD thesis, University of Cambridge, 2014.
  20. AtoMig: Automatically Migrating Millions Lines of Code from TSO to WMM. In Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2, ASPLOS 2023, Vancouver, BC, Canada, March 25-29, 2023 (2023), T. M. Aamodt, N. D. E. Jerger, and M. M. Swift, Eds., ACM, pp. 61–73.
  21. Foundations of the C++ Concurrency Memory Model. In Proceedings of the 29th ACM SIGPLAN Conference on Programming Language Design and Implementation (New York, NY, USA, 2008), PLDI ’08, Association for Computing Machinery, p. 68–78.
  22. Validating Optimizations of Concurrent C/C++ Programs. In Proceedings of the 2016 International Symposium on Code Generation and Optimization (New York, NY, USA, 2016), CGO ’16, ACM, pp. 216–226.
  23. Grounding Thin-air Reads with Event Structures. Proc. ACM Program. Lang. 3, POPL (Jan. 2019), 70:1–70:28.
  24. A Survey of Compiler Testing. ACM Comput. Surv. 53, 1 (Feb. 2020).
  25. Colin, S. RC11 Memory Model. https://github.com/herd/herdtools7/blob/master/herd/libdir/rc11.cat, 2022. Accessed: 2022-06-30.
  26. Cook, S. A. The Complexity of Theorem-Proving Procedures. In Proceedings of the Third Annual ACM Symposium on Theory of Computing (New York, NY, USA, 1971), STOC ’71, ACM, p. 151–158.
  27. Armv8 AArch64 Memory Model. https://github.com/herd/herdtools7/blob/master/herd/libdir/aarch64.cat, 2021.
  28. Dijkstra, W. Bug 108891 - libatomic: AArch64 SEQ_CST 16-byte load missing barrier. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108891.
  29. Compositional Verification of Compiler Optimisations on Relaxed Memory. In Programming Languages and Systems (Cham, 2018), A. Ahmed, Ed., Springer International Publishing, pp. 1027–1055.
  30. Automated Testing of Graphics Shader Compilers. Proc. ACM Program. Lang. 1, OOPSLA (Oct. 2017).
  31. Volatiles Are Miscompiled, and What to Do About It. In Proceedings of the 8th ACM International Conference on Embedded Software (New York, NY, USA, 2008), EMSOFT ’08, ACM, pp. 255–264.
  32. BMC for Weak Memory Models: Relation Analysis for Compact SMT Encodings. 07 2019, pp. 355–365.
  33. GCC-Mailing-List. [PATCH, AArch64 v2 05/11] aarch64: Emit LSE stop instructions. https://gcc.gnu.org/legacy-ml/gcc-patches/2018-10/msg01960.html, 2018. Accessed: 2020-13-06.
  34. GCC-Mailing-List. [PATCH, AArch64 v2 05/11] aarch64: Emit LSE stop instructions. https://gcc.gnu.org/legacy-ml/gcc-patches/2018-10/msg02042.html, 2018. Accessed: 2020-13-06.
  35. Geeson, L. Added dmb ish to arm model. https://github.com/herd/herdtools7/pull/385, 2022. Accessed: 2022-11-26.
  36. Geeson, L. [AArch64]: 128-bit Const Atomic Load implemented using Store Pair instruction, induces Runtime Crash on Arm AArch64. https://github.com/llvm/llvm-project/issues/61770, 2023.
  37. Geeson, L. [AArch64]: 128-bit seq_cst load can be reordered before prior RMW operations under LSE and above. https://github.com/llvm/llvm-project/issues/62652, 2023. Accessed: 2023-05-11.
  38. Geeson, L. [AArch64]: Atomic Exchange Allows Reordering past Acquire Fence . https://github.com/llvm/llvm-project/issues/68428, 2023.
  39. Geeson, L. [AArch64][CodeGen]: LD{AX}P/S{LX}TP endian swap. https://github.com/llvm/llvm-project/issues/61431, 2023.
  40. Geeson, L. branch delay slots are not filled with atomic stores. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110573, 2023.
  41. CAAT: Consistency as a Theory. Proc. ACM Program. Lang. 6, OOPSLA2 (oct 2022).
  42. Status report: Broken dependency orderings in the linux kernel. https://lpc.events/event/16/contributions/1174/, 2022. Accessed: 2022-26-11.
  43. Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations. In MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture (New York, NY, USA, 2021), MICRO ’21, ACM, p. 679–694.
  44. Intel. Pin. https://www.intel.com/content/www/us/en/developer/articles/tool/pin-a-dynamic-binary-instrumentation-tool.html, 2013.
  45. ISO-C-Std, O. ISO/IEC 9899:201x. https://www.open-std.org/jtc1/sc22/wg14/www/docs/n2912.pdf, 2022. Accessed: 2023-11-10.
  46. CCmutator: A Mutation Generator for Concurrency Constructs in Multithreaded C/C++ Applications. In Proceedings of the 28th IEEE/ACM International Conference on Automated Software Engineering (2013), ASE’13, IEEE Press, p. 722–725.
  47. Repairing Sequential Consistency in C/C++11. PLDI 2017, ACM, pp. 618–632.
  48. Lamport, L. How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs. IEEE Trans. Comput. 28, 9 (Sept. 1979), 690–691.
  49. Dreaming up Metamorphic Relations: Experiences from Three Fuzzer Tools. In 2021 IEEE/ACM 6th International Workshop on Metamorphic Testing (MET) (2021), pp. 61–68.
  50. Compiler Validation via Equivalence modulo Inputs. SIGPLAN Not. 49, 6 (June 2014), 216–226.
  51. Leroy, X. Formal Verification of a Realistic Compiler. Commun. ACM 52, 7 (July 2009), 107–115.
  52. Many-Core Compiler Fuzzing. In Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation (New York, NY, USA, 2015), PLDI ’15, ACM, p. 65–76.
  53. LLVM. AArch64 Dead register definitions. https://llvm.org/docs/doxygen/AArch64DeadRegisterDefinitionsPass_8cpp_source.html.
  54. LLVM-Bugzilla. [AArch64] atomicrmw on Armv8.1-a memory ordering can be changed. https://bugs.llvm.org/show_bug.cgi?id=35094, 2019. Accessed: 2020-13-06.
  55. LLVM-Phabricator. [AArch64] Fix for bug 35094 atomicrmw on Armv8.1-A+lse. https://reviews.llvm.org/D58348, 2019.
  56. LLVM-Phabricator. AAArch64: use ldp/stp for 128-bit atomic load/store in v.84 onwards. https://reviews.llvm.org/rG13aa102e07695297fd17f68913c343c95a7c56ad, 2021.
  57. LLVM-Phabricator. Add support for LDAPR. https://reviews.llvm.org/D126250, 2022. Accessed: 2022-11-22.
  58. LLVM-Phabricator. [WoA] Use fences for sequentially consistent stores/writes. https://reviews.llvm.org/D141748, 2023.
  59. Alive2: Bounded Translation Validation for LLVM. Association for Computing Machinery, New York, NY, USA, 2021, p. 65–79.
  60. Maranget, L. RISC-V Memory Model. https://github.com/herd/herdtools7/blob/master/herd/libdir/riscv.cat, 2022.
  61. Maranget, L. ARM model vs. AArch32 model. https://cambium.inria.fr/~maranget/cats7/aarch32/, 2023.
  62. IBM PowerPC Memory Model. https://github.com/herd/herdtools7/blob/master/herd/libdir/ppc.cat, 2022.
  63. MIPS Memory Model. https://github.com/herd/herdtools7/blob/master/herd/libdir/mips.cat, 2023.
  64. x86-64 Memory Model. https://github.com/herd/herdtools7/blob/master/herd/libdir/x86tso-mixed.cat, 2023.
  65. Compiler Testing via a Theory of Sound Optimisations in the C11/C++11 Memory Model. In Proceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation (New York, NY, USA, 2013), PLDI ’13, ACM, pp. 187–196.
  66. Nimal, V. P. J. Static analyses over weak memory. PhD thesis, University of Oxford, UK, 2014.
  67. On the Small-Scope Hypothesis for Testing Answer-Set Programs. In Proceedings of the Thirteenth International Conference on Principles of Knowledge Representation and Reasoning (2012), KR’12, AAAI Press, p. 43–53.
  68. Bridging the Gap between Programming Languages and Hardware Weak Memory Models. Proc. ACM Program. Lang. 3, POPL’19 (Jan. 2019).
  69. Lasagne: A Static Binary Translator for Weak Memory Model Architectures. In Proceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation (New York, NY, USA, 2022), PLDI 2022, Association for Computing Machinery, p. 888–902.
  70. Understanding POWER Multiprocessors. PLDI ’11, ACM, pp. 175–186.
  71. The Semantics of x86-CC Multiprocessor Machine Code. In Proceedings of the 36th Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (New York, NY, USA, 2009), POPL ’09, ACM, pp. 379–391.
  72. Tange, O. Gnu parallel - the command-line power tool. ;login: The USENIX Magazine 36, 1 (Feb 2011), 42–47.
  73. Common Compiler Optimisations Are Invalid in the C11 Memory Model and What We Can Do About It. POPL ’15, ACM, pp. 209–220.
  74. CompCertTSO: A Verified Compiler for Relaxed-Memory Concurrency. J. ACM 60, 3 (June 2013).
  75. Automatically Comparing Memory Consistency Models. POPL 2017, ACM, pp. 190–204.
  76. C4: The C Compiler Concurrency Checker. In Proceedings of the 30th ACM SIGSOFT International Symposium on Software Testing and Analysis (New York, NY, USA, 2021), ISSTA 2021, ACM, p. 670–673.
  77. High-coverage metamorphic testing of concurrency support in C compilers. Software Testing, Verification and Reliability (2022), e1812.
  78. Finding and Understanding Bugs in C Compilers. In Proceedings of the 32nd ACM SIGPLAN Conference on Programming Language Design and Implementation (New York, NY, USA, 2011), PLDI ’11, ACM, pp. 283–294.
User Edit Pencil Streamline Icon: https://streamlinehq.com
Authors (2)
  1. Luke Geeson (3 papers)
  2. Lee Smith (3 papers)
Citations (1)