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ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation (2310.09977v3)

Published 15 Oct 2023 in cs.CR and cs.AR

Abstract: We introduce ABACuS, a new low-cost hardware-counter-based RowHammer mitigation technique that performance-, energy-, and area-efficiently scales with worsening RowHammer vulnerability. We observe that both benign workloads and RowHammer attacks tend to access DRAM rows with the same row address in multiple DRAM banks at around the same time. Based on this observation, ABACuS's key idea is to use a single shared row activation counter to track activations to the rows with the same row address in all DRAM banks. Unlike state-of-the-art RowHammer mitigation mechanisms that implement a separate row activation counter for each DRAM bank, ABACuS implements fewer counters (e.g., only one) to track an equal number of aggressor rows. Our evaluations show that ABACuS securely prevents RowHammer bitflips at low performance/energy overhead and low area cost. We compare ABACuS to four state-of-the-art mitigation mechanisms. At a near-future RowHammer threshold of 1000, ABACuS incurs only 0.58% (0.77%) performance and 1.66% (2.12%) DRAM energy overheads, averaged across 62 single-core (8-core) workloads, requiring only 9.47 KiB of storage per DRAM rank. At the RowHammer threshold of 1000, the best prior low-area-cost mitigation mechanism incurs 1.80% higher average performance overhead than ABACuS, while ABACuS requires 2.50X smaller chip area to implement. At a future RowHammer threshold of 125, ABACuS performs very similarly to (within 0.38% of the performance of) the best prior performance- and energy-efficient RowHammer mitigation mechanism while requiring 22.72X smaller chip area. ABACuS is freely and openly available at https://github.com/CMU-SAFARI/ABACuS.

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Citations (11)
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Summary

  • The paper introduces ABACuS, an innovative RowHammer mitigation method that shares row activation counters across different memory banks to enhance scalability.
  • ABACuS significantly reduces chip area requirements by using a single counter to track maximum activations for sibling rows across banks.
  • Evaluation shows ABACuS achieves minimal performance overhead (0.58% at threshold 1000) and storage cost while maintaining effectiveness against low RowHammer thresholds.

ABACuS: All-Bank Activation Counters for Scalable and Low-Overhead RowHammer Mitigation

The paper "ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation" tackles the persistent security issue known as the RowHammer vulnerability in modern DRAM systems. RowHammer arises when repeated activation of a row in a DRAM can cause bit flips in neighboring rows, potentially leading to security exploits. As DRAM technology continues to scale, the RowHammer threshold (the minimum number of activations required to induce a bit flip) has decreased significantly, necessitating effective and scalable mitigation techniques.

Problem Context and ABACuS Solution

Traditional mitigation strategies often rely on row activation counters to track and manage potential aggressor rows, but face key scalability issues, particularly with increasing DRAM density and the number of banks. Many current mechanisms either incur high area costs due to the necessity of numerous activation counters or suffer from substantial performance penalties when RowHammer thresholds are low.

ABACuS (All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation) introduces an innovative approach that involves sharing row activation counters across banks. This method leverages the common observation that workloads frequently access rows with the same address in different banks around the same time, thus reducing the need for as many counters while ensuring efficient tracking of the most frequently activated rows.

Key Mechanisms

At its core, ABACuS uses a single activation counter to track the worst-case (maximum) number of activations across all sibling rows (rows with the same address in different banks). This design choice considerably reduces the chip area needed to implement the mitigation strategy, as the number of counters is minimized, directly correlating with a significant decrease in resource use per bank.

The ABACuS system periodically resets its counters based on the refresh window, ensuring all rows are refreshed in a timely manner to prevent potential bit flips before a RowHammer threshold is reached. Additionally, ABACuS adjusts smoothly to different DRAM configurations and varied application workloads due to its adaptive nature.

Evaluation and Results

In extensive evaluations against prominent existing solutions like Graphene and Hydra, ABACuS demonstrates robust performance across a range of benchmarks and RowHammer thresholds. Notably, at a RowHammer threshold of 1000, ABACuS achieves a performance overhead of merely 0.58% for single-core workloads and requires only 18.93 KiB of storage, indicating remarkable efficiency.

Furthermore, ABACuS exhibits exceptional scalability even when the threshold is as low as 125, maintaining low performance overheads while still offering significant area savings compared to other state-of-the-art approaches. The evaluation shows that the shared activation counters approach effectively tracks aggressor rows with reduced mitigation actions and unnecessary refreshes, thus minimizing overheads.

Implications and Future Developments

ABACuS represents a substantial advancement in DRAM RowHammer mitigation techniques, offering a scalable, low-cost solution that balances performance, energy efficiency, and minimal area impact. Its architecture aligns well with modern DRAM system requirements, addressing both present and future challenges posed by decreasing RowHammer thresholds.

Looking forward, ABACuS opens pathways for further integration with emerging DRAM technologies and potentially developing cross-layer solutions that combine hardware and software enhancements to bolster security. Additionally, future research could explore the integration of ABACuS with system-level protections to create a more holistic defense mechanism against RowHammer-induced vulnerabilities.

In summary, ABACuS stands out as an efficient, scalable approach to RowHammer mitigation that can be feasibly deployed in next-generation DRAM systems, making it a compelling choice for both current and future computing environments.

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