Papers
Topics
Authors
Recent
Gemini 2.5 Flash
Gemini 2.5 Flash
119 tokens/sec
GPT-4o
56 tokens/sec
Gemini 2.5 Pro Pro
43 tokens/sec
o3 Pro
6 tokens/sec
GPT-4.1 Pro
47 tokens/sec
DeepSeek R1 via Azure Pro
28 tokens/sec
2000 character limit reached

Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU (2309.00381v2)

Published 1 Sep 2023 in cs.DC

Abstract: The Sophon SG2042 is the world's first commodity 64-core RISC-V CPU for high performance workloads and an important question is whether the SG2042 has the potential to encourage the HPC community to embrace RISC-V. In this paper we undertaking a performance exploration of the SG2042 against existing RISC-V hardware and high performance x86 CPUs in use by modern supercomputers. Leveraging the RAJAPerf benchmarking suite, we discover that on average, the SG2042 delivers, per core, between five and ten times the performance compared to the nearest widely available RISC-V hardware. We found that, on average, the x86 high performance CPUs under test outperform the SG2042 by between four and eight times for multi-threaded workloads, although some individual kernels do perform faster on the SG2042. The result of this work is a performance study that not only contrasts this new RISC-V CPU against existing technologies, but furthermore shares performance best practice.

Definition Search Book Streamline Icon: https://streamlinehq.com
References (16)
  1. RAJA: Portable performance for large-scale scientific applications. In 2019 ieee/acm international workshop on performance, portability and productivity in hpc (p3hpc). IEEE, 71–81.
  2. eProcessor project 2023. eProcessor: an open source full stack ecosystem. Retrieved Aug 16, 2023 from https://eprocessor.eu/
  3. Esperanto Technologies 2023. Esperanto: Outstanding solutions for Generative AI and HPC. Retrieved Aug 16, 2023 from https://www.esperanto.ai/
  4. Evaluation of compilers’ capability of automatic vectorization based on source code analysis. Scientific Programming 2021 (2021), 1–15.
  5. RISC-V based virtual prototype: An extensible and configurable platform for the system-level. Journal of Systems Architecture 109 (2020), 101756.
  6. Richard D Hornung and Holger E Hones. 2017. Raja performance suite. Technical Report. Lawrence Livermore National Lab.(LLNL), Livermore, CA (United States).
  7. Ricardo Jesus. [n. d.]. Check for A Study on the Performance Implications of AArch64 Atomics Ricardo Jesus () and Michèle Weiland EPCC, The University of Edinburgh, Edinburgh, UK. In High Performance Computing: 38th International Conference, ISC High Performance 2023, Hamburg, Germany, May 21–25, 2023, Proceedings. Springer Nature, 279.
  8. Ricardo Jesus and Michèle Weiland. 2022. ChapelPerf: A Performance Suite for Chapel. In The Annual Chapel Implementers and Users Workshop.
  9. Seamless compiler integration of variable precision floating-point arithmetic. In 2021 IEEE/ACM International Symposium on Code Generation and Optimization (CGO). IEEE, 65–76.
  10. Backporting risc-v vector assembly. arXiv preprint arXiv:2304.10324 (2023).
  11. Test-driving RISC-V Vector hardware for HPC. arXiv preprint arXiv:2304.10319 (2023).
  12. Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study. arXiv preprint arXiv:2306.01797 (2023).
  13. Open chip community 2023. Open XuanTie C906. Retrieved Aug 16, 2023 from https://xrvm.com/cpu-details?id=4056751997003636736
  14. Coyote: An open source simulation tool to enable RISC-V in HPC. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 130–135.
  15. rvv-next 2023. GNU compiler collection. Retrieved Aug 16, 2023 from https://github.com/riscv-collab/riscv-gnu-toolchain/tree/rvv-next
  16. StarFive 2023. SoC Platform. Retrieved Aug 16, 2023 from https://www.starfivetech.com/en/site/soc
User Edit Pencil Streamline Icon: https://streamlinehq.com
Authors (4)
  1. Nick Brown (67 papers)
  2. Maurice Jamieson (12 papers)
  3. Joseph Lee (14 papers)
  4. Paul Wang (4 papers)
Citations (4)

Summary

Evaluating the Sophon SG2042 RISC-V CPU: An Insight into Its HPC Potential

The paper "Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU" critically assesses the performance of the Sophon SG2042 CPU, providing a detailed analysis of its applicability and competitiveness in the field of High-Performance Computing (HPC). This research elucidates the potential shift toward RISC-V architecture within HPC environments by comparing this novel CPU against both existing RISC-V hardware and established x86 CPUs prevalent in current supercomputing systems.

Key Highlights and Findings

The Sophon SG2042 represents a significant advancement by introducing a 64-core RISC-V processor aimed explicitly at high-performance workloads. The paper employs the RAJAPerf benchmarking suite to explore the SG2042's performance capabilities against its RISC-V contemporaries, like the SiFive VisionFive V1 and V2, equipped with U74 cores. The findings illustrate a striking performance improvement, where the SG2042's XuanTie C920 core delivers, on average, between five and ten times better performance in single-precision calculations compared to the U74 core. For double-precision tasks, the C920 shows three to six times better performance than its predecessor.

The research further explores the threading and vectorisation attributes of the SG2042. It is evident that optimal thread placement, taking into account NUMA regions and core clusters, is crucial for harnessing its full potential. The performance benefits of vectorisation are more pronounced with single-precision tasks, highlighting RVV (RISC-V Vector extension) advantages, albeit limited by current compiler capabilities and vector length specifics.

In comparing with x86 CPUs, the SG2042 demonstrates commendable multi-threaded performance, albeit overshadowed by robust competition from chips like the AMD Rome EPYC 7742, Intel Broadwell, and Ice Lake processors. Although the SG2042 lags behind in certain benchmarks, particularly those leveraging AVX and AVX-512 instruction sets, it shows competitiveness against older architectures such as Intel's Sandybridge.

Implications and Future Perspectives

The performance insight presented in this paper indicates the Sophon SG2042 as a critical milestone in RISC-V's journey towards HPC adoption. While the SG2042 does not yet rival top-tier x86 processors in terms of raw performance, it provides a base for future RISC-V developments that could, with enhancements in vectorisation support and architectural refinements, bring RISC-V into closer competitiveness with existing HPC stalwarts.

Future efforts could focus on the development of compiler support for RVV v1.0, enabling a more seamless transition and optimum utilisation of available vectorisation capabilities. Further exploration on distributed memory and MPI performance could also shed light on the SG2042's capabilities in large-scale HPC applications.

This paper serves as a foundational paper for the HPC community to assess serious RISC-V hardware candidates, indicating that although RISC-V has not reached parity with x86 equivalents, the gap narrows continuously. Continued architectural enhancements, coupled with strategic software developments, might well position RISC-V as a formidable competitor in the ever-evolving HPC landscape.