DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips (2211.05838v5)

Abstract: To understand and improve DRAM performance, reliability, security and energy efficiency, prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art open source infrastructures capable of conducting such studies are obsolete, poorly supported, or difficult to use, or their inflexibility limit the types of studies they can conduct. We propose DRAM Bender, a new FPGA-based infrastructure that enables experimental studies on state-of-the-art DRAM chips. DRAM Bender offers three key features at the same time. First, DRAM Bender enables directly interfacing with a DRAM chip through its low-level interface. This allows users to issue DRAM commands in arbitrary order and with finer-grained time intervals compared to other open source infrastructures. Second, DRAM Bender exposes easy-to-use C++ and Python programming interfaces, allowing users to quickly and easily develop different types of DRAM experiments. Third, DRAM Bender is easily extensible. The modular design of DRAM Bender allows extending it to (i) support existing and emerging DRAM interfaces, and (ii) run on new commercial or custom FPGA boards with little effort. To demonstrate that DRAM Bender is a versatile infrastructure, we conduct three case studies, two of which lead to new observations about the DRAM RowHammer vulnerability. In particular, we show that data patterns supported by DRAM Bender uncovers a larger set of bit-flips on a victim row compared to the data patterns commonly used by prior work. We demonstrate the extensibility of DRAM Bender by implementing it on five different FPGAs with DDR4 and DDR3 support. DRAM Bender is freely and openly available at https://github.com/CMU-SAFARI/DRAM-Bender.

• The paper introduces DRAM Bender as a versatile, FPGA-based infrastructure that allows arbitrary DRAM command control for in-depth experimental research.
• It employs a modular design supporting multiple DRAM standards and simplifies testing through a user-friendly C++ and Python API.
• Case studies demonstrate its capability to uncover new insights into DRAM vulnerabilities, such as RowHammer effects and undocumented in-DRAM operations.

Evaluation of the DRAM Bender Infrastructure for DRAM Testing

The paper presents DRAM Bender, a comprehensive FPGA-based infrastructure designed to facilitate experimental research on state-of-the-art DRAM chips. This infrastructure aims to address the limitations of existing solutions by offering a highly versatile, easy-to-use, and extensible platform for conducting diverse DRAM studies. The paper articulates the design features and explores the implications of DRAM Bender's applicability in DRAM research, detailing several case studies that underscore its utility in uncovering new insights into DRAM behavior.

Key Features of DRAM Bender

The infrastructure overcomes the constraints of earlier DRAM testing platforms by offering several critical features:

1. Direct Interface Exposure: DRAM Bender enables low-level command issuance to DRAM chips, thereby allowing for arbitrary command sequencing and timing modifications. This feature facilitates detailed investigations into DRAM operations that would otherwise be infeasible using standard commercial setups.
2. Modular and Extensible Design: The FPGA-based infrastructure employs a modular setup, allowing for easy adaptation to support various DRAM standards such as DDR3 and DDR4. It is designed to be adaptable to new FPGA boards with minimal effort, which significantly broadens its applicability.
3. Ease of Use: The infrastructure integrates a user-friendly C++ and Python API, which simplifies the development of DRAM testing programs. The API allows for streamlined experiment development and execution, lowering the entry barrier for researchers not deeply familiar with FPGA programming.

Case Studies and Observations

The paper presents three distinct case studies illustrating the capabilities of DRAM Bender:

1. RowHammer Interleaving Patterns: This paper investigates the impact of activation patterns of aggressor rows on RowHammer vulnerabilities. The results indicate that the pattern of interleaving activations critically affects the susceptibility of DRAM cells to bit flips, presenting new insights into crafting and defending against RowHammer attacks.
2. Influence of Data Patterns on RowHammer: By leveraging DRAM Bender’s capability to program arbitrary data patterns, the paper shows that more comprehensive data patterns facilitate the detection of additional RowHammer-induced bit flips that would not be identified using traditional methodologies.
3. In-DRAM Bitwise Operations: This case demonstrates the execution of processing-in-memory operations, like bitwise AND/OR, in contemporary DDR4 devices. The paper underscores the potential of DRAM Bender to explore undocumented processing capabilities inherent in modern DRAM architectures.

Implications and Future Directions

DRAM Bender’s design offers significant implications for both the technical community and practical DRAM evaluations. By democratizing access to experimental DRAM research tools, it potentially accelerates the development of new strategies to enhance DRAM performance, security, and reliability.

Future work could focus on extending support to upcoming DRAM standards like DDR5, which promises to include novel mechanisms for enhanced robustness against issues like RowHammer. Additionally, integrating DRAM Bender with power measurement setups could pave the way for more accurate studies on DRAM power dynamics.

Overall, DRAM Bender provides a robust and open-source testing infrastructure that promises to significantly enhance the paper of memory technologies, thereby contributing to more reliable and efficient systems as demands on memory technology scale with advancing computational needs.